Digital FSK Decoding Using Envelope Comparison for Noise Rejection
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Solution Overview
Problem
Existing FSK decoding methods face complexity and cost issues when dealing with closely spaced frequencies and high baud rates, especially in noisy environments, and require dedicated tone decoder devices that are sensitive to aging and temperature variations.
Innovation Solution
The implementation of FSK decoding using envelope comparison in the digital domain, which generates multiple clocks and frequency envelopes to accurately decode FSK signals, eliminating the need for phase lock loops and dedicated tone decoders, and allowing for programmable frequency settings and noise rejection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated tone decoder devices are used for FSK decoding, then decoding accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces analog/dedicated tone decoder devices with a digital signal processing approach using a field programmable gate array (FPGA). The FPGA implements FSK decoding through digital logic circuits that generate frequency envelopes and compare incoming signals against these envelopes, eliminating the need for dedicated analog tone decoder hardware while maintaining decoding accuracy.
2Measurement precision
If dedicated tone decoder devices are used for FSK decoding, then decoding accuracy is improved, but cost increases
Solution Approach 1:
The patent uses a field programmable gate array (FPGA) which is a reconfigurable digital logic device that can be programmed to implement FSK decoding functionality. This approach replaces expensive dedicated analog tone decoder devices with a more cost-effective digital implementation that can be configured through software, reducing manufacturing costs while maintaining decoding accuracy.
3Productivity
If FSK decoding is implemented for closely spaced frequencies and high baud rates, then communication capability is improved, but decoder design complexity increases
Solution Approach 1:
The patent implements a dynamic FSK decoder design using an FPGA that can be reconfigured through software to handle different frequency spacings and baud rates. The decoder generates frequency envelopes dynamically based on programmable parameters, allowing it to adapt to various communication standards and requirements without requiring hardware redesign, thus managing complexity while maintaining communication capability.
4Reliability
If dedicated tone decoder devices are used, then FSK decoding performance is improved, but adaptability to frequency variance and lock-in time customization is reduced
Solution Approach 1:
The patent creates a universal FSK decoder using an FPGA that can handle multiple FSK communication standards and configurations. The decoder is programmed with configurable frequency envelopes and timing parameters that can be adjusted through software to match different communication requirements, making it adaptable to various frequency variances and lock-in time requirements while maintaining reliable FSK decoding performance across different applications.
Data Source
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AI summary
A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) (101) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated by clock generator (115) including a first clock and second clock framing a logic '0' level of the FSK signal, and a third clock and fourth clock framing a logic '1' level of the FSK signal. At least four frequency envelops are generated from the clocks by envelop generator (120) including a logic '0' envelop, a logic '1' envelop, a lower frequency envelop below the logic '0' envelop, and an upper frequency envelop above the logic '1' envelop. R'Edge is compared to the four envelops by comparator (125), and a decoded output (130) is produced, logic '0' if the R'Edge overlaps the logic '0' envelop, logic '1' if R'Edge overlaps the logic '1' envelop, and a previous output state if R'Edge does not overlap the logic '0' or logic '1' envelop.