Digital Glitch Detection with Process and Temperature Compensation
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Solution Overview
Problem
Existing glitch detection systems in data processing systems face challenges in differentiating between harmless noise and malicious glitches, particularly in advanced process nodes like 16 nm FinFET, and are not capable of effectively detecting short-duration voltage glitches, leading to potential device instability and security breaches.
Innovation Solution
A digital glitch security detection system using a delay line to monitor supply voltage glitches, with digital post-processing to compare measurement results against a reference value, generating an error signal for significant deviations, and compensating for manufacturing and temperature variations, allowing for continuous protection without the need for duplicate delay lines or analog sensors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog sensors are used for glitch detection, then detection capability is improved, but portability to advanced process nodes and integration difficulty worsen
Solution Approach 1:
The patent replaces analog sensors with a fully digital glitch detection mechanism implemented using standard digital logic cells. The delay line, composed of digital logic elements, substitutes the analog sensing approach, enabling seamless integration into advanced digital process nodes while maintaining glitch detection capability through digital signal processing.
2Measurement precision
If glitch filters are made more sensitive to detect short-duration glitches, then detection precision is improved, but false detection of harmless noise increases
Solution Approach 1:
The patent implements a feedback mechanism where the glitch detector continuously monitors delay line output and compares it against reference values. The system uses hysteresis and adaptive thresholding based on historical data to distinguish genuine glitches from noise, reducing false detections while maintaining sensitivity to short-duration attacks.
Solution Approach 2:
The detection thresholds and reference values are made dynamic rather than static. The system adapts to changing environmental conditions by continuously updating reference values based on measured delay variations, allowing the detector to maintain optimal sensitivity while accommodating normal operational variations and noise.
3Reliability
If process and temperature variations are compensated for, then detection reliability is improved, but system complexity increases
Solution Approach 1:
The patent implements self-service compensation where the delay line itself is used to measure and compensate for process and temperature variations. By monitoring the delay variations under different conditions and using this information to adjust reference values, the system achieves environmental compensation without requiring separate complex compensation circuits or additional sensors.
4Area of stationary object
If a single delay line is used instead of duplicate delay lines, then area overhead is reduced, but measurement accuracy may be impacted
Solution Approach 1:
The patent makes the single delay line multi-functional by using it for both glitch detection and environmental characterization. The same delay line structure serves dual purposes: detecting voltage glitches through delay variation and simultaneously providing data for process and temperature compensation, eliminating the need for separate reference delay lines while maintaining measurement accuracy.
Data Source
AI summary
A fully digital method and apparatus are provided for detecting glitches on a monitored line by providing a toggle signal to an initial delay circuit and a plurality of delay elements formed with standard logic cells so that logic values from the delay elements are captured in a corresponding plurality of clocked capture flops to provide a digitized representation of a delay value during a sampling period which is converted to a numerical measurement result which is evaluated against a reference value to generate an output error signal if a difference between the numerical measurement result and reference value exceeds a programmable margin, where the initial delay circuit is configured with a trim setting to impose an initial delay to compensate for process variations and where the reference value is adapted over a plurality of sampling periods to compensate for temperature effects on the numerical measurement result.