Digital IC Delay Prediction Using Dilated CNN and BLSTM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for delay prediction in integrated circuits at multiple corners are inefficient due to the complexity of path delay variations with process, voltage, and temperature, leading to long design cycles and potential chip failures, as conventional machine learning methods struggle to model sequence structure data and handle mesh delay data effectively.
Innovation Solution
A method utilizing a dilated convolutional neural network (Dilated CNN) to associate delays at adjacent combinations of temperature and voltage, a bi-directional long short-term memory neural network (BLSTM) to model topology information, and a multi-gate mixture-of-experts network (MMoE) to combine delay and topology information for simultaneous prediction of path delays across multiple corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tens of thousands of condition combinations of process, voltage, and temperature are simulated to reduce chip failure risk, then reliability is improved, but design cycle time increases excessively
Solution Approach 1:
The patent performs preliminary simulation at selected corners (extreme process, voltage, and temperature conditions) to establish baseline delay values before manufacturing. This preliminary action allows the system to predict delays at unsimulated corners through interpolation, avoiding the need to simulate all tens of thousands of condition combinations while still ensuring chip reliability across the full operating range.
Solution Approach 2:
The patent creates a computational model that copies and generalizes delay characteristics from simulated corners to unsimulated corners. By modeling the relationships between process, voltage, temperature, and delay, the system can predict delays at any corner based on simulations from a limited set of corners, effectively copying delay patterns without direct simulation of each corner.
2Ease of operation
If conventional machine learning methods use matrix format data input for delay prediction, then ease of operation is improved, but measurement precision deteriorates due to inability to model sequence structure data
Solution Approach 1:
The patent transforms the conventional matrix format data input into a three-dimensional tensor structure that incorporates sequence information. By adding a temporal or sequential dimension to the data representation, the model can capture the ordered relationships in circuit paths and delay variations, significantly improving prediction accuracy while maintaining ease of operation through automated tensor construction.
3Ease of manufacture
If conventional machine learning methods expand mesh delay data into one-dimensional vectors for modeling, then ease of manufacture is improved, but loss of information increases leading to limited model accuracy
Solution Approach 1:
The patent maintains the multi-dimensional structure of mesh delay data by representing it as tensors rather than flattening to one-dimensional vectors. This preserves the spatial and relational information inherent in the mesh structure, allowing the model to learn from adjacent corner relationships and deliver dependencies while maintaining modeling simplicity through standardized tensor operations.
4Ease of manufacture
If cell library is provided only near nominal voltage by foundry, then ease of manufacture is improved, but adaptability deteriorates as timing verification at wide voltages cannot be met
Solution Approach 1:
The patent uses interpolation and modeling techniques to copy and generalize cell delay characteristics from the nominal voltage cell library to low voltage conditions. By establishing relationships between voltage, process, temperature, and delay, the system can predict cell behavior at voltages where no actual cell library data exists, enabling timing verification across wide voltage ranges without requiring additional foundry cell library provisions.
Data Source
AI summary
Disclosed in the present invention is a method for predicting a delay at multiple corners for a digital integrated circuit, which is applicable to the problem of timing signoff at multiple corners. In the aspect of feature engineering, a path delay relationship at adjacent corners is extracted by using a dilated convolutional neural network (Dilated CNN), and learning is performed by using a bi-directional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) to obtain topology information of a path. Finally, prediction results of a path delay at a plurality of corners are obtained by using an output of a multi-gate mixture-of-experts network model (Multi-gate Mixture-of-Experts, MMoE). Compared with a conventional machine learning method, the present invention can achieve prediction with higher precision through more effective feature engineering processing in a case of low simulation overheads, and is of great significance for timing signoff at multiple corners of a digital integrated circuit.