Digital Input Filter Circuit for Short-Pulse Noise Rejection
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Solution Overview
Problem
Existing noise reduction circuits fail to effectively remove noise signals that have different levels and widths shorter than the sampling cycle when mixed with digital input signals at successive sampling points, leading to incorrect identification of noise as normal signals.
Innovation Solution
A filter circuit comprising an input-signal processing section that samples and holds digital input signals, reversing the signal when the level changes between sampling points, and a signal-level determining section that delays and compares the signals to distinguish between noise and normal signals based on level consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If noise reduction circuit samples input signal based only on signal level at sampling point, then circuit structure is simple, but noise signals with width shorter than sampling cycle are output as normal signals
Solution Approach 1:
The patent segments the signal analysis into multiple delay stages (first delay circuit, second delay circuit, etc.) that examine the signal at different time points. This segmentation allows the circuit to detect whether a signal level change is transient noise or a genuine signal by comparing across multiple time intervals, thereby improving noise removal accuracy without significantly increasing overall circuit complexity.
Solution Approach 2:
The patent applies preliminary action by using delay circuits to pre-process the signal before final noise determination. The signal is delayed through multiple stages to create time-staggered versions that are then compared by logic circuits. This preliminary time-based processing enables the system to identify and filter noise pulses before they can corrupt the output, improving reliability while maintaining manageable circuit complexity.
2Measurement precision
If noise signals with different levels are successively mixed with input signal at successive sampling points, then noise width appears constant, but output signal level is reversed and noise is output as normal signal
Solution Approach 1:
The patent divides the signal detection process into multiple segmented delay stages, where each stage examines the signal at a different time offset. Logic circuits then compare the signal levels across these segments to determine if a level change represents noise or a genuine signal transition. This segmented approach prevents misidentification of successively mixed noise signals by analyzing the temporal pattern across multiple segments.
Solution Approach 2:
The patent implements feedback through logic circuits that continuously monitor and compare signal levels across multiple delay stages. When a noise pulse is detected (identified by inconsistent level changes across delay stages), the system provides feedback to suppress the erroneous output. This feedback mechanism ensures that noise signals with varying levels are correctly identified and filtered, maintaining high reliability in signal level detection.
Data Source
AI summary
A filter circuit includes an input-signal processing section and a signal-level determining section. The input-signal processing section samples and holds a digital input signal input according to a clock signal, outputs the holding signal as a sampling input signal when a level of the digital input signal is constant between sampling points, and reverses the holding signal and outputs the reversed signal as the sampling input signal when the level of the digital input signal changes between the sampling points. The signal-level determining section sequentially delays the sampling input signal from the input-signal processing section into plural stages, outputs a first level signal at a first level when all the delayed signals are at the first level, and outputs a second level signal at a second level when all the delayed signals are at the second level.