Digital Integrator Circuit for Boost Converter Voltage Regulation
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Solution Overview
Problem
Achieving stable output voltage regulation in boost converters is challenging due to the need for high DC loop gain, which often requires large on-chip capacitance, leading to undesirable semiconductor capacitor sizes and instability issues.
Innovation Solution
A digital integrator circuit with two comparators and a counter that can count up, count down, and pause, coupled with a digital-to-analog converter (DAC) to provide feedback adjustment signals, allowing for stable output voltage regulation without the need for large on-chip capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If very high DC loop gain is used to achieve high DC accuracy in a boost converter, then voltage regulation accuracy is improved, but the required on-chip capacitance increases to nano farad range which is undesirable
Solution Approach 1:
The patent changes the operating parameters of the integrator circuit by positioning the pole at a specific frequency (1/4 to 1/5 times the unity gain bandwidth) rather than at DC, and introduces a zero at DC through the capacitor-connected switch. This parameter transformation allows achieving high DC loop gain without requiring large on-chip capacitance, as the pole-zero configuration provides the necessary gain characteristics with much smaller capacitor values.
Solution Approach 2:
The patent introduces an intermediary mechanism - a switch connected to a capacitor - that mediates between the need for high DC loop gain and the constraint of limited on-chip capacitance. The switch periodically connects the capacitor to ground, creating a pole-zero pair that amplifies the DC loop gain effect without requiring the capacitor to be continuously large, thus resolving the contradiction between gain accuracy and capacitance area.
2Stability of the object's composition
If a capacitance of the order of nano farads is used on chip to realize the necessary zero location for good phase margin, then phase margin is improved, but the semiconductor capacitor size becomes undesirable
Solution Approach 1:
The patent transforms the parameter relationship by positioning the pole at a frequency (1/4 to 1/5 times UGB) rather than at DC, and creating a DC zero through the capacitor-switch configuration. This parameter transformation allows the system to achieve the necessary phase margin with much smaller capacitor values than would be required in a conventional DC-integrator configuration, thereby reducing the semiconductor capacitor area from nano farad range to manageable sizes.
3Reliability
If large on-chip capacitance is used to achieve high DC loop gain, then voltage regulation stability is improved, but the device area and cost increase
Solution Approach 1:
The patent changes the fundamental parameters of the integrator by introducing a frequency-dependent pole position (1/4 to 1/5 times UGB) and a DC zero, replacing the conventional DC pole configuration. This parameter transformation enables the system to achieve high DC loop gain and stable voltage regulation with significantly reduced capacitance values, thereby reducing device area and associated costs while maintaining regulation stability.
Data Source
AI summary
An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.