Digital I/O Pin Analog Sensing Using Pulse-Count ADC Circuit

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Solution Overview

Problem

Conventional systems require a separate ADC block in each controller or FPGA, leading to increased design overhead and power consumption due to the need for multiple ADC ICs, which limits the design flexibility and efficiency in converting analog signals to digital signals.

Innovation Solution

A digital I/O pin analog signal sensing architecture that utilizes a difference amplifier, comparator, divide-by-2 counter, and AND gates to convert analog signals into digital signals, eliminating the need for separate ADC ICs by outputting a digital signal that can be used to reconstruct analog values, thereby reducing circuit resources and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a separate ADC block is included in each controller or FPGA, then analog signal conversion capability is provided, but design overhead and power consumption increase

Engineering Contradiction:
Improveanalog signal conversion capabilityVSAvoiddesign overhead
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a shared ADC resource that can be accessed by multiple controllers and FPGAs through a common bus interface. Instead of each controller having its own dedicated ADC block, a single ADC module serves multiple devices, allowing one component to perform multiple functions for different controllers, thereby reducing overall system complexity and design overhead while maintaining analog signal conversion capability across all devices

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines multiple ADC functions into a single shared ADC module that serves multiple controllers and FPGAs. By merging the ADC resources into a common shared component with a multiplexed interface, the system reduces the total number of ADC blocks needed, eliminating redundant functionality and simplifying the overall system architecture while still providing analog-to-digital conversion capability to all connected devices

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If a separate ADC block is included in each controller or FPGA, then analog signal conversion capability is provided, but power consumption increases

Engineering Contradiction:
Improveanalog signal conversion capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The shared ADC module is designed to be accessed by multiple controllers and FPGAs through time-multiplexed operations. Only one converter is actively performing analog-to-digital conversion at any given moment, while other devices can enter low-power states or perform other tasks, significantly reducing the total power consumption compared to having multiple simultaneously operating ADC blocks in each controller

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements periodic time-multiplexed access to the shared ADC module by different controllers and FPGAs. The ADC operates in periodic intervals serving different devices sequentially, allowing non-active devices to reduce their operational state and power consumption, while still maintaining the capability to perform analog signal conversion when needed

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If conventional ADC blocks are used in each controller, then analog to digital conversion is achieved, but circuit resources are inefficiently utilized

Engineering Contradiction:
Improveanalog to digital conversionVSAvoidcircuit resources
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The shared ADC module provides full-precision analog-to-digital conversion capability that is accessible by multiple controllers and FPGAs. The converter maintains high measurement precision through proper reference voltage management and conversion algorithms, while the shared resource model eliminates the need for multiple identical ADC blocks, thereby optimizing circuit resource utilization without sacrificing conversion accuracy

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the number of ADCs required, optimizes sampling time and resolution, and allows for more efficient use of FPGA resources, enabling flexible design and significant power savings in both AC and DC applications.

Implementation Method 1

Conventional ADCs include a difference amplifier module that computes the voltage difference generated across pins connected to an analog circuit

Methodology Applied
Scientific EffectVoltage difference computation: Ohm's Law

Implementation Method 2

An analog to digital converter (ADC) is a system that converts an analog signal into a digital signal. For example, an ADC may convert an analog voltage or current to a digital number representing the magnitude of the voltage or current

Methodology Applied
Scientific EffectAnalog to digital conversion:

Data Source

PatentEP3754855A1Sensing analog signal through digital I/O pins
Publication Date: 2020.12.23 ROSEMOUNT AEROSPACE INC
  • EP3754855A1 patent drawingFigure 1A~1B
  • EP3754855A1 patent drawingFigure 2
  • EP3754855A1 patent drawingFigure 3

AI summary

Systems and methods for sensing an analog signal through digital input/output (I/O) pins are provided. Aspects include an analog to digital (ADC) circuit configured to generate a digital signal based on observations of the analog signal obtained from an analog circuit, where the ADC circuit includes a difference amplifier, a comparator, a divideby2 counter and two AND gates. Aspects also include a controller (102) including a pin configured to receive the digital signal. The controller is configured to count pulses within the digital signal and determine values corresponding to the analog signal based on the counted pulses.