Digital I/Q Demodulation With Fixed-Rate ADC Noise Rejection
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Solution Overview
Problem
Existing signal demodulation techniques face challenges with noise interference, particularly in digital devices with touch-sensitive displays, leading to inefficiencies and errors due to the inability to accurately measure both real and imaginary components of signals, and requiring complex analog multipliers and filters.
Innovation Solution
A digital demodulation method using a fixed sampling rate ADC, which multiplies input signals with in-phase and quadrature coefficients to produce demodulated signals, allowing for accurate measurement of both components and simplifying device design by eliminating the need for analog components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog multipliers and filters are used for signal demodulation, then measurement precision of signal components is improved, but device complexity increases
Solution Approach 1:
The patent replaces analog multipliers and filters with digital signal processing operations. The analog signal path is substituted with digital multiplication by sine and cosine coefficients followed by digital accumulation, eliminating complex analog components while maintaining measurement precision for both real and imaginary components of the signal.
Solution Approach 2:
The patent changes the domain of signal processing from analog to digital. By converting the analog signal to digital form and performing demodulation through digital multiplication with pre-calculated coefficients and digital accumulation, the system achieves precise measurement of signal components without requiring complex analog circuitry.
2Adaptability or versatility
If sampling time of ADC is changed to adjust demodulation frequency, then adaptability of demodulator is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent makes the demodulation frequency adjustable through digital means rather than changing the fixed ADC sampling rate. By dynamically selecting different sine and cosine coefficients for demodulation while maintaining a constant sampling clock, the system achieves frequency adaptability without requiring precision adjustments to the ADC timing circuitry.
Solution Approach 2:
The patent separates the sampling rate parameter from the demodulation frequency parameter. The ADC operates at a fixed sampling rate for manufacturing simplicity, while the demodulation frequency is adjusted by changing the digital coefficients used in the multiplication stage, thereby achieving adaptability without compromising manufacturing precision.
3Measurement precision
If complex analog demodulation circuitry is used, then signal processing accuracy is improved, but cost of device increases
Solution Approach 1:
The patent substitutes expensive analog demodulation circuitry including analog multipliers and filters with inexpensive digital logic operations. The signal processing accuracy is maintained through digital multiplication by coefficients and digital accumulation, which can be implemented efficiently in standard digital logic or software, significantly reducing device cost.
Solution Approach 2:
The patent uses pre-calculated digital copies of sine and cosine waveforms as coefficients for demodulation. These coefficient tables can be stored in memory and reused multiple times, replacing the need for continuous analog waveform generation and reducing both component count and cost while maintaining processing accuracy.
Data Source
AI summary
A device includes an analog to digital converter configured to convert voltages into a digital signal by sampling the voltages at a fixed sampling time; a first multiplier configured to multiply the digital signal with in-phase coefficients, the in-phase coefficients generated to produce a demodulated in-phase signal at a demodulation signal frequency; a first adder configured accumulate the demodulated in-phase signal to output in-phase magnitude values; a second multiplier configured to multiply the digital signal with quadrature coefficients, the quadrature coefficients generated to produce a demodulated quadrature signal at the demodulation signal frequency; and a second adder configured to accumulate the demodulated quadrature signal to output quadrature magnitude values.