Digital Jitter Termination in Repeater Circuits Without PLLs
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Solution Overview
Problem
Traditional repeaters in digital communication systems transfer low-frequency jitter to downstream links, exceeding jitter tolerance and causing bit errors, and existing jitter termination mechanisms using phase-locked loops (PLLs) are costly and introduce additional analog artifacts.
Innovation Solution
A repeater circuit with a clock and data recovery stage, a filter stage using a digital low-pass filter and phase interpolators to generate a filtered clock signal, and a memory component to sample and store data, decoupling jitter tracking from jitter transfer without the need for PLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional repeater circuits are used to track low-frequency jitter, then jitter tracking capability is improved, but jitter transfer to downstream links increases causing bit errors
Solution Approach 1:
The patent segments the jitter handling function into two independent parts: jitter tracking (for reliability) and jitter transfer (for downstream quality). By using separate clock signals - one for sampling (tracking jitter) and another for output (minimizing jitter transfer), the system achieves both goals simultaneously without the traditional coupling that caused the contradiction.
Solution Approach 2:
The patent introduces an intermediary mechanism - a jitter cleaning circuit with a low-pass filter and phase interpolator - that sits between the input signal processing and output signal generation. This intermediary tracks the necessary jitter information while filtering out harmful high-frequency components before output, effectively mediating between jitter tracking requirements and jitter transfer problems.
2Reliability
If phase-locked loops (PLLs) are used for jitter termination, then jitter filtering capability is improved, but circuit area and cost increase
Solution Approach 1:
The patent replaces expensive, complex PLL-based jitter termination circuits with a simpler, more compact implementation using a low-pass filter and phase interpolator. This alternative approach achieves the same jitter filtering function with significantly reduced circuit area and lower cost, effectively substituting a 'cheap' solution for the 'expensive' traditional approach.
Solution Approach 2:
The patent substitutes the mechanical/analog PLL system with a digital signal processing approach using low-pass filtering and phase interpolation. This replacement of the traditional PLL mechanism with digital processing elements reduces circuit complexity and area while maintaining jitter filtering effectiveness.
3Reliability
If phase-locked loops (PLLs) are used for jitter termination, then jitter filtering capability is improved, but additional analog artifacts are introduced reducing jitter tolerance
Solution Approach 1:
The patent replaces the analog PLL system with a digital low-pass filter and phase interpolator implementation. This substitution eliminates the analog artifacts (phase noise and jitter) that are inherent to PLL operation, while still achieving effective jitter filtering through digital signal processing techniques.
Solution Approach 2:
The patent uses a simpler digital filtering approach instead of complex analog PLL circuitry, which inherently introduces fewer harmful artifacts. The digital implementation provides cleaner signal processing without the analog noise and jitter that plague traditional PLL-based solutions.
Data Source
AI summary
A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.