Digital LDO Regulator Hybrid Event Time Control
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Solution Overview
Problem
Analog LDO regulators face challenges with high power consumption and stability issues due to amplifiers, while digital LDO regulators struggle with long response times and settling times, especially when trying to eliminate or reduce the size of output capacitors for high-speed operations.
Innovation Solution
A digital LDO regulator is developed using a hybrid control method that combines event-driven and time-driven schemes, where an event-driven circuit asynchronously detects voltage deviations and generates trigger signals, and a time-driven circuit synchronizes with a clock to generate error signals and control the output voltage, improving response and settling times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog LDO regulator uses an amplifier for voltage regulation, then the regulation stability is improved, but the power consumption increases and the response speed decreases
Solution Approach 1:
The patent replaces the analog amplifier-based voltage regulation system with a digital control system. The digital LDO regulator uses a control logic unit that processes digital error signals to generate control signals for the pass transistor, eliminating the need for analog amplifiers and their associated power consumption and stability issues.
Solution Approach 2:
The patent implements a feedback mechanism where the output voltage is continuously monitored, compared with the reference voltage, and the error signal is processed by the control logic unit. This closed-loop feedback system maintains regulation stability without requiring power-hungry analog amplifiers.
2Speed
If a digital LDO regulator eliminates or reduces output capacitors for high-speed operation, then the response time is improved, but the settling time increases
Solution Approach 1:
The patent employs dynamic control by adjusting the operating mode of the digital LDO regulator based on system conditions. The control logic unit can switch between different control strategies (e.g., proportional control, integral control) to optimize both response time and settling time, allowing fast response without excessive capacitor size while maintaining adequate settling performance.
3Measurement precision
If a digital LDO regulator uses synchronous feedback control with fixed clock cycle, then the control precision is improved, but the response speed to voltage deviations decreases
Solution Approach 1:
The patent uses periodic sampling of the output voltage at fixed clock cycles for precise measurement, while also incorporating event-driven detection that can trigger control actions between sampling points. This hybrid approach maintains measurement precision through regular sampling while improving response speed through event-triggered updates when voltage deviations occur.
4Speed
If an event-driven circuit asynchronously detects voltage deviations, then the response speed is improved, but the control precision decreases
Solution Approach 1:
The patent merges synchronous feedback control and event-driven feed-forward control into a unified digital control system. The synchronous component provides precise periodic measurement and control, while the event-driven component detects voltage deviations asynchronously and triggers immediate control responses. The control logic unit integrates both error signals to generate the final control signal, combining the advantages of both approaches.
Data Source
AI summary
A digital Low Drop-Out regulator includes: an event-driven circuit for generating a trigger signal by asynchronously detecting whether an output voltage is out of a threshold range to generate a first error information signal and a first control signal; a time-driven circuit for generating a second error information signal by detecting a change in the output voltage synchronized with a clock signal, and generating a second control signal by combining the first and second error information signals; a clock/trigger control circuit for generating the clock signal having a first or second cycle based on the trigger signal and the first and second error information signals; a first array driver for controlling driving force of the output voltage in response to the first control signal; and a second array driver for controlling the driving force of the output voltage in response to the second control signal.