Digital LDO Regulator With Charge Accumulation for Low-Voltage Ripple
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Solution Overview
Problem
Conventional on-chip voltage regulators, particularly low-dropout (LDO) regulators, face challenges in maintaining proper operation at low supply voltages and achieving efficient power management with minimal voltage ripple and power consumption.
Innovation Solution
A digital logic voltage regulator design that employs a voltage comparator to control a PMOS power switch with a small delay, using a ratioed logic comparator and a charge accumulator to limit output voltage drift from a target voltage, thereby minimizing voltage ripple and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional LDO regulator with PMOS transistor and analog operational amplifier is used, then clean regulated voltage ripple is achieved, but the error amplifier cannot operate properly when supplied voltage is below 0.6 V
Solution Approach 1:
The patent replaces the analog operational amplifier with a digital logic comparator that uses digital logic circuits (AND gates, OR gates, NOT gates) to perform voltage comparison and control functions. This substitution enables proper operation at low supply voltages below 0.6V where analog amplifiers fail, while maintaining voltage regulation capability through digital control of the PMOS pass transistor.
2Adaptability or versatility
If a digital LDO with clocked comparator and synchronous shift register circuits is used, then low voltage operation is enabled, but more delay is introduced which affects transient response and consumes more power
Solution Approach 1:
The patent removes the synchronous shift register circuit from the conventional digital LDO architecture, retaining only the essential digital logic comparator and PMOS pass transistor. This extraction eliminates the delay introduced by the shift register while maintaining low-voltage operation capability through the simplified digital logic control path.
Solution Approach 2:
Instead of using a clocked comparator that operates synchronously with a clock signal (introducing clock cycle delays), the patent employs an asynchronous digital logic comparator that responds immediately to voltage changes. This inversion of the timing approach eliminates clock-related delays and improves transient response speed.
3Loss of energy
If a switched converter is used, then high power efficiency is achieved, but high voltage ripple is produced which is unacceptable for RF and analog blocks
Solution Approach 1:
The patent introduces a digital logic comparator as an intermediary control element between the voltage reference and the PMOS pass transistor. This intermediary provides precise voltage comparison and digital control that enables better regulation performance with lower output voltage ripple compared to switched converters, while maintaining high power efficiency through minimal quiescent current consumption in the digital logic circuit.
Data Source
AI summary
Digital logic voltage regulators and related methods generate a regulated voltage via controlled switching of a power transistor. A digital logic voltage regulator includes a voltage level comparator, a power transistor, and a charge accumulator. The voltage level comparator generates a digital control signal that alternates between a first voltage level and a second voltage level in response to changes in relative voltage level between the regulated output voltage and the target voltage. The digital control signal causes the power transistor to switch from off to on in response to a reduction of the regulated output voltage relative to the target voltage and causes the power transistor to switch from on to off in response to an increase of the regulated output voltage relative to the target voltage. The charge accumulator decreases variation in the regulated output voltage that would occur without the charge accumulator.