Digital LDO Comparator Using Edge Detection for Fast Low-Power Regulation
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Solution Overview
Problem
Conventional digital LDO regulators face challenges in achieving ultra-low power consumption and fast transient response while maintaining a large load dynamic range, often requiring large coupling capacitors or power-hungry components, which limits voltage supply range and increases noise levels in subthreshold SoC designs.
Innovation Solution
A digital comparator system coupled with pull-up and pull-down resistors, featuring edge detector stages that control the resistors based on clock signal edges, reducing power consumption and enabling a large load dynamic range with a small on-chip capacitor, thus expanding the voltage supply range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional digital LDO regulators use large coupling capacitors or internal charge pumps to achieve fast transient response, then transient response speed is improved, but voltage supply range is narrowed and device size increases
Solution Approach 1:
The patent extracts and eliminates the large coupling capacitors and internal charge pumps from the LDO regulator design. By removing these components, the voltage supply range is no longer constrained by their operational requirements, allowing the LDO to function across a broader voltage range while maintaining fast transient response through the digital comparator's edge detection mechanism
Solution Approach 2:
The patent replaces the traditional analog capacitor-based transient response mechanism with a digital comparator system that uses edge detection of clock signals. This substitution eliminates the need for large physical capacitors and charge pumps, enabling fast transient response through digital signal processing rather than analog energy storage and transfer
2Speed
If multiple-clock or dynamic-clock schemes are used to improve transient response, then transient response is improved, but power consumption increases significantly
Solution Approach 1:
The patent employs periodic clock signals with specific rising and falling edges to trigger the digital comparator's edge detection circuits. This periodic action enables the system to achieve fast transient response only when needed (at clock edges) rather than continuously operating multiple-clock schemes, thereby significantly reducing overall power consumption while maintaining rapid response capability
Solution Approach 2:
The digital comparator automatically detects edges of the clock signals and triggers the pull-up or pull-down resistors without requiring external control logic or additional power-hungry support blocks. The system serves itself by using the inherent edges of the clock signals to drive the transient response, eliminating the need for power-intensive control mechanisms
3Object-affected harmful factors
If dynamic dead zone control is used to reduce noise, then noise performance is improved, but transient response settling time increases
Solution Approach 1:
The patent applies partial action by using pull-up and pull-down resistors that are activated only during specific clock signal edges through the edge detection mechanism. This allows the system to achieve noise reduction through controlled resistor activation while maintaining fast transient response, as the resistors provide decisive voltage transitions rather than requiring long dead zone settling periods
Data Source
AI summary
This disclosure relates to a digital comparator coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to an output terminal of a low dropout (LDO) regulator. In particular, the digital comparator comprises an edge detector module, a consecutive two-edge detector module and a consecutive three-edge detector module whereby the edge detector module is configured to receive two clock signals as inputs and after being processed by these three modules, to pull-up or pull-down the resistors at the output terminal of the LDO regulator based on the rising and falling edges of the received clock signals.