Clock-Synchronized Digital LDO DAC Transitions to Reduce Limit Cycling
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Solution Overview
Problem
Existing digital low dropout regulators (LDOs) experience significant limit cycling due to rapid state transitions of the DAC code signals, which affect performance and increase power supply rejection ratio (PSRR) sensitivity.
Innovation Solution
Implementing a digital LDO with a first digital to analog converter that synchronizes state transitions of the DAC code signal to occur after multiple clock cycles, reducing the frequency of transitions during normal operation and employing a panic mode with a fast clock during exceptional conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the DAC code signal transitions rapidly between states to respond quickly to load changes, then the response speed improves, but limit cycling increases and PSRR sensitivity deteriorates
Solution Approach 1:
The patent implements a clocked transition mechanism where DAC code transitions occur only at specific clock edges rather than continuously. The transition timing is synchronized to the clock signal, creating periodic action that prevents arbitrary rapid switching. This reduces limit cycling by ensuring transitions happen in a controlled, periodic manner rather than continuously responding to every error signal change.
Solution Approach 2:
The patent uses a transition trigger that is prepared in advance and only activates under specific conditions. The clock signal serves as a pre-established timing reference, and transitions are permitted only when both the error signal indicates a need for change and the clock signal permits it. This preliminary preparation of transition conditions prevents spontaneous rapid transitions that cause limit cycling.
2Measurement precision
If the DAC code signal transitions frequently to maintain accurate output voltage, then the voltage accuracy improves, but voltage ripple increases under steady-state loads
Solution Approach 1:
By restricting DAC transitions to occur only at clock edges, the patent creates periodic action that spacing out transitions in time. This periodic timing prevents continuous or frequent transitions that would cause voltage ripple, while still maintaining adequate voltage accuracy by ensuring transitions occur when needed and permitted by the clock cycle.
Solution Approach 2:
The patent employs feedback through the error signal that continuously monitors the difference between reference and output voltages. This feedback mechanism ensures transitions occur only when voltage accuracy requires correction, preventing unnecessary transitions that would generate ripple. The combination of feedback control and clock-synchronized timing maintains accuracy while minimizing harmful voltage ripple.
3Speed
If the clock frequency is increased to improve transient response, then the response time improves, but limit cycling and instability increase
Solution Approach 1:
The patent uses periodic clock signals to gate DAC transitions, creating a rhythm that stabilizes the system. Even at higher frequencies, the periodic nature ensures transitions occur in a predictable, regular pattern rather than chaotically, maintaining stability. The periodic action provides a natural frequency reference that prevents the instability and excessive limit cycling that would result from uncontrolled rapid transitions.
4Adaptability or versatility
If the DAC transitions are allowed to occur at every clock cycle for maximum responsiveness, then the adaptability improves, but PSRR sensitivity increases
Solution Approach 1:
The patent implements periodic gating of DAC transitions using the clock signal, which spaces transitions in time rather than allowing continuous adaptation. This periodic action reduces PSRR sensitivity by preventing high-frequency transitions that would amplify power supply noise, while still maintaining adequate adaptability to respond to genuine load changes that occur at the clock rate or slower.
Data Source
AI summary
A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the digital LDO being synchronized to a clock signal and comprising a first digital to analog converter configured to generate a first DAC code signal, the output voltage being dependent the first DAC code signal, trigger state transitions of the first DAC code signal between states, and for at least a portion of the state transitions of the first DAC code signal, trigger each subsequent state transition after more clock cycles of the clock signal than for the preceding state transition.