Digital LDO Panic Mode Mean-Code Control for Limit Cycling
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Solution Overview
Problem
Existing digital low dropout regulators (LDOs) experience significant limit cycling at the end of the fast clocking period, which affects the stability and accuracy of the output voltage.
Innovation Solution
A digital LDO that includes a comparison circuit, a first digital to analog converter (DAC) operable in a panic mode, and a panic circuit. The DAC calculates a mean value of the generated DAC code signal during a panic mode and sets the DAC code signal to this mean value, reducing limit cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the DAC operates in panic mode with fast clocking to quickly respond to output voltage deviations, then the response speed is improved, but limit cycling occurs at the end of the fast clocking period causing stability degradation
Solution Approach 1:
The system performs preliminary action by detecting panic conditions (output voltage deviations) early through the panic circuit and immediately activating fast clocking mode. This allows the DAC to proactively adjust the output voltage before the deviation becomes significant, improving response speed while the mean value calculation at the end of fast clocking prevents subsequent limit cycling and maintains stability.
2Measurement precision
If the DAC code signal is continuously adjusted during panic mode to track the error signal, then the accuracy of output voltage regulation is improved, but oscillatory behavior (limit cycling) develops at the end of the fast clocking period
Solution Approach 1:
The system uses feedback by continuously monitoring the error signal between the reference voltage and feedback voltage during panic mode. The DAC code signal is adjusted based on this feedback to maintain accurate output voltage regulation. At the end of fast clocking, the mean value of the DAC code signal is calculated and applied to eliminate limit cycling, ensuring operational reliability while maintaining precision.
3Productivity
If the clock speed is increased during panic conditions to accelerate the correction of output voltage errors, then the correction speed is improved, but the system experiences timed period limitations and residual oscillations after the panic mode ends
Solution Approach 1:
The system implements periodic action by operating in distinct modes: fast clocking mode during panic conditions and normal clocking mode afterward. The fast clocking accelerates correction during the panic period, while the subsequent calculation and application of the mean DAC code signal value ensures smooth transition and eliminates residual oscillations, minimizing overall settling time without sacrificing correction speed.
Data Source
AI summary
A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage comprising a comparison circuit configured to receive the reference voltage, receive a feedback voltage, the feedback voltage being dependent on the output voltage, compare the reference voltage and the feedback voltage, and generate an error signal that is dependent on the comparison between the reference voltage and the feedback voltage, a first digital to analog converter configured to be operable in a panic mode in which the first digital to analog converter is configured to receive the error signal, generate a first DAC code signal based on the error signal for a first time period, the output voltage being dependent on the first DAC code signal, and calculate a mean value of the generated first DAC code signal during at least a portion of the first time period, and set the first DAC code signal to the mean value as calculated, a panic circuit configured to detect when the feedback voltage exceeds a first threshold value or falls below a second threshold value, and control the first digital to analog converter to operate in the panic mode when the feedback voltage exceeds the first threshold value or falls below the second threshold value.