Digital LDO Regulator Control for Fast Load Transients
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Solution Overview
Problem
Low Drop-Out (LDO) regulators face challenges in maintaining stable output voltage and efficiency, particularly when load current changes abruptly or is small, due to limitations in analog voltage headroom and frequency stability.
Innovation Solution
The proposed LDO regulator incorporates a voltage-to-time converter, driving time-to-current converter, slew adjusting circuit, and compensation time-to-current converter to generate voltage pulse signals that drive the output node digitally, reduce voltage headroom, and enhance stability by employing slew adjusting and compensation currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an LDO regulator is designed with traditional analog control, then it can provide stable output voltage, but it suffers from limited voltage headroom and poor frequency stability when load current changes abruptly
Solution Approach 1:
The patent replaces the traditional analog control system with a digital control system. The voltage-to-time converter (VTC) converts the voltage error signal into a time-domain pulse width signal, and the time-to-current converter (TIC) converts this time signal back to current to drive the pass transistor. This digital approach allows for faster response to load current changes while maintaining output voltage stability, resolving the contradiction between reliability and adaptability.
Solution Approach 2:
The patent changes the operating parameters of the control system by introducing a voltage-to-time converter that transforms the continuous voltage error signal into a discrete time-domain pulse width signal. This parameter transformation enables the system to respond more effectively to abrupt load current changes while maintaining stable output voltage, thereby improving both reliability and adaptability.
2Loss of energy
If the LDO regulator uses digital voltage control, then voltage headroom is reduced, but frequency stability may be compromised
Solution Approach 1:
The patent incorporates a compensation time-to-current converter (compensation TIC) that provides frequency compensation feedback to the control system. This feedback mechanism ensures that the digital control approach maintains frequency stability while operating with reduced voltage headroom, resolving the contradiction between energy efficiency and reliability.
Solution Approach 2:
The patent introduces a compensation TIC as an intermediary element between the digital control components and the output stage. This intermediary provides the necessary frequency compensation to maintain stability, allowing the system to benefit from reduced voltage headroom while preserving frequency stability through the mediating compensation mechanism.
3Use of energy by moving object
If the LDO regulator operates with small load currents, then power consumption is reduced, but output voltage stability deteriorates
Solution Approach 1:
The patent employs dynamic control through the VTC and TIC that automatically adjusts the control signal characteristics based on the instantaneous load conditions. When load current is small, the digital control mechanism maintains appropriate drive levels to ensure output voltage stability while keeping power consumption low, resolving the contradiction between energy efficiency and reliability across varying load conditions.
Data Source
AI summary
A low drop-out (LDO) regulator includes a voltage-to-time converter (VTC) responsive to a reference voltage and an output voltage. The VTC generates a voltage pulse signal having: (i) a sign associated with a magnitude of the output voltage relative to a magnitude of the reference voltage, and (ii) a first pulse width proportional to a difference the output voltage and the reference voltage. A driving time-to-current converter (TIC) drives a gate node with a non-zero driving current proportional to the first pulse width of the voltage pulse signal. A slew adjusting circuit drives the gate node with a non-zero slew adjusting current, in response to the first pulse width of the voltage pulse signal being equal to or greater than reference time interval. A compensation TIC drives the output node with a non-zero compensation current having a magnitude proportional to the first pulse width of the voltage pulse signal.