Digital LDO Regulator With Asynchronous PMOS Binary Search

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional digital LDO regulators face challenges in achieving fast transient response performance across a wide output current range, making it difficult to implement high integration and high performance in power management integrated circuits.

Innovation Solution

A digital LDO regulator utilizing a binary-weighted PMOS array that performs asynchronous binary search, with a mode determining unit operating in fine, coarse, and medium modes based on output voltage, and employing multiple comparators to control the PMOS array operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional digital-based search algorithm is used, then the LDO regulator can operate across a wide output current range, but the transient response performance is slow

Engineering Contradiction:
Improvetransient response performanceVSAvoidtime complexity
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent divides the output current range into multiple segments and uses different search algorithms for different segments. For low output current ranges, an asynchronous binary search algorithm is employed, while for high output current ranges, a conventional digital-based search algorithm is used. This segmentation allows the system to achieve fast transient response in low current ranges while maintaining wide output current range coverage across all segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically switches between different search algorithms based on the output current range. The mode determining unit monitors the output current and selects the appropriate search algorithm (asynchronous binary search or conventional digital-based search) in real-time. This dynamic adaptation enables the LDO regulator to optimize transient response performance according to the actual operating conditions.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If the LDO regulator uses a single search algorithm, then the system complexity is low, but the transient response performance cannot be optimized across different output current ranges

Engineering Contradiction:
Improveperformance optimization across output current rangesVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a dynamic mode switching mechanism that automatically selects between asynchronous binary search mode and conventional digital-based search mode based on the output current range. The mode determining unit monitors the output current and switches algorithms in real-time, providing adaptability across different operating conditions while maintaining a relatively simple system architecture through unified control logic.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The LDO regulator is designed with multi-functionality by incorporating both asynchronous binary search capability and conventional digital-based search capability within a single unified system. The mode determining unit and switching mechanism enable the system to perform multiple search operations depending on the output current range, making the regulator adaptable to various operating conditions without requiring separate dedicated circuits for each mode.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11747846B2Digital LDO regulator for performing asynchronous binary search using binary-weighted PMOS array and operation method thereof
Publication Date: 2023.09.05 KOREA UNIV RES & BUSINESS FOUND
  • US11747846B2 patent drawing
  • US11747846B2 patent drawing
  • US11747846B2 patent drawing

AI summary

Disclosed is a digital LDO regulator capable of performing asynchronous binary search using a binary-weighted PMOS array. The digital LDO regulator includes a PMOS array unit including a binary-weighted PMOS array and that binary searches the PMOS array asynchronously, and a mode determining unit that operates in at least one of a fine mode, a coarse mode, and a medium mode, based on an output voltage of the PMOS array unit.