Digital Synthesizable LDO Regulator for SoC Power Management
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Solution Overview
Problem
Existing low dropout (LDO) regulator architectures face challenges such as dependence on analog voltage for gate drive, which does not scale well with process technologies, stability issues due to package parasitic effects, and finite DC offset errors, leading to inefficiencies and design complexities, especially in dual loop architectures.
Innovation Solution
The implementation of a digital synthesizable low dropout regulator (DLDO) with multiple voltage identification (VID) signals, allowing for independent power supply management of processor cores within a System-on-Chip (SoC), using a power control unit to generate external and internal VIDs, and a DLDO VR with power-gate transistors controlled by a digital bus, enabling reprogrammable coefficients and soft start capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If analog voltage control is used in LDO regulator, then the regulator can operate with simple circuitry, but the design does not scale well with process technologies and exhibits stability issues
Solution Approach 1:
The patent replaces the analog voltage control mechanism with a digital control system. The digital LDO regulator uses a controller that receives a digital representation of the output voltage and generates digital control signals for the power gate transistors, eliminating the need for analog feedback circuits and their associated stability issues.
Solution Approach 2:
The patent changes the control parameter from analog voltage to digital voltage representation. The controller processes digital voltage representations and generates corresponding digital control signals, enabling better scaling with process technologies while maintaining control functionality.
2Power
If analog LDO architecture is used, then the regulator can provide voltage regulation, but it exhibits minimum dropout voltage (50mV to 100mV) that becomes a challenge when input power supplies are getting lower
Solution Approach 1:
The patent implements dynamic control of the power gate transistors through digital signals. The controller can dynamically adjust the gate control signals based on the input voltage conditions, enabling the regulator to adapt to lower input voltages and reduce the dropout voltage dynamically rather than being fixed by analog circuit design.
3Power
If analog LDO is used, then voltage regulation can be achieved, but finite DC offset error due to gain limitations affects DC set point accuracy
Solution Approach 1:
The patent substitutes the analog feedback mechanism with a digital one. The controller receives a digital representation of the output voltage and processes it to generate precise control signals, eliminating the gain limitations and DC offset errors inherent in analog circuits while maintaining voltage regulation functionality.
4Power
If dual loop architecture is used in analog LDO, then voltage regulation can be improved, but integration and design challenges increase
Solution Approach 1:
The patent replaces the complex dual loop analog architecture with a digital control system. The controller processes digital voltage representations and generates digital control signals, simplifying the integration process while maintaining or improving voltage regulation performance through digital signal processing capabilities.
Data Source
AI summary
Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.