Digital LDO Regulator Parallel Control Loop Latency
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Solution Overview
Problem
Conventional digital LDO regulators face challenges in achieving short control loop latency while maintaining low power consumption, which is essential for efficient voltage regulation in modern electronic devices, particularly in system-on-chip (SoC) applications.
Innovation Solution
The event-driven digital LDO regulator employs a parallel scheme with separate proportional and integral control units, utilizing an analog-to-digital converter to generate error codes and control signals, and power transistor arrays to adjust the output voltage, thereby reducing control loop latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional digital LDO regulator designs are used, then power consumption is reduced, but control loop latency increases
Solution Approach 1:
The control loop is segmented into separate proportional and integral control units that operate in parallel. The proportional control unit processes error codes immediately for fast response, while the integral control unit accumulates error over time for steady-state accuracy. This segmentation allows the system to achieve short control loop latency through the proportional path without requiring high power consumption for continuous integral processing.
Solution Approach 2:
The regulator uses event-driven periodic sampling of the output voltage through the ADC, rather than continuous monitoring. Control signals are generated only when voltage regulation is needed, reducing power consumption while maintaining fast response when adjustments are required. The periodic nature of the control updates allows the system to balance between rapid response and energy efficiency.
2Speed
If analog LDO regulator is used, then high-speed operation is achieved, but bandwidth must be set great which complicates design
Solution Approach 1:
The patent replaces the analog amplifier-based control system with a digital control system. Instead of using continuous analog signals and complex bandwidth compensation networks, the system uses digital error codes from an ADC and generates discrete control signals through logical operations. This substitution simplifies the design by eliminating the need for careful bandwidth setting while maintaining high-speed operation through direct digital control of the power transistor arrays.
Solution Approach 2:
The system changes the control parameters from continuous analog voltage levels to discrete digital error codes. The ADC converts the output voltage error into a digital code that can be processed through simple logical operations in the proportional and integral control units. This parameter change from analog to digital domain simplifies the control mechanism while enabling fast response times without complex bandwidth considerations.
3Power
If digital LDO regulator is used, then great voltage decrease capability is achieved, but control loop latency increases
Solution Approach 1:
The control functionality is segmented into proportional and integral units that operate in parallel. The proportional control unit provides immediate response to voltage errors by directly modulating the power transistor arrays, enabling fast voltage adjustment. The integral unit handles steady-state precision by accumulating error over time. This segmentation allows great voltage decrease capability through the proportional path without suffering from the latency that would occur if a single sequential control mechanism were used.
Solution Approach 2:
The patent merges the proportional and integral control functions into a unified digital control architecture that processes error codes simultaneously through both paths. The control signals from both units are combined to drive the power transistor arrays, allowing the system to achieve both fast transient response (great voltage decrease capability) and steady-state accuracy without the latency penalty of sequential processing.
Data Source
AI summary
A regulator includes: an ADC for detecting a change in an output voltage and outputting an error code; a control signal generation unit for generating a proportional control signal, integral control signals, a counting signal, and an error sign signal based on the error code; a proportional control unit for shifting the error code based on a proportional gain factor, and outputting a first control signal by synchronizing the shifted error code with the proportional control signal; an integral control unit for shifting the integral control signals based on the counting signal, shifting the shifted signals based on an integral gain factor to generate integral pulse signals, and outputting second control signals by controlling a pre-stored code value based on the integral pulse signals and the error sign signal; and a driving unit for outputting first and second currents in response to the first and second control signals.