Digital LDO Regulator Step-Back Control for SoC Power Stability
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Solution Overview
Problem
The increasing number of functions in system-on-chip (SoC) leads to a higher need for power routings between the power management integrated circuit (PMIC) and SoC, resulting in increased area and cost on printed circuit boards, and existing digital LDO regulators face stability issues due to delays in detecting output voltage changes.
Innovation Solution
A digital low-dropout (LDO) regulator with an LDO core that selects control modes based on output voltage states, using header cell switches to adjust supply current stepwise, performing step-back and negative step operations to stabilize output voltage and reduce droop, thereby reducing power consumption and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of power routings between PMIC and SoC is increased to support more functions, then the power supply capability is improved, but the area and cost of PCB are increased
Solution Approach 1:
The patent merges multiple power supply functions into a single LDO regulator embedded within the SoC. Instead of having separate power routings from PMIC to different IP blocks, the LDO regulator consolidates power management by receiving a single merged power supply and generating multiple different voltages for various IP blocks internally, thereby reducing PCB area while maintaining power supply capability.
2Area of stationary object
If a single merged power supply is provided to multiple IP blocks to reduce power routings, then the PCB area is reduced, but the power consumption is increased
Solution Approach 1:
The LDO regulator segments the merged power supply into multiple different voltage outputs tailored to each IP block's requirements. By dividing the single power supply into multiple specialized voltage rails, the system reduces power waste that would occur if all blocks received the same voltage, thereby reducing overall power consumption while maintaining the reduced PCB area benefit.
Solution Approach 2:
The patent applies local quality by providing different voltages to different IP blocks based on their specific requirements. Each IP block receives the optimal voltage for its operation, rather than a uniform voltage, which improves power efficiency and reduces overall power consumption while maintaining the consolidated power routing structure.
3Speed
If digital LDO regulator operates at high speed to respond to voltage changes, then the response time is improved, but stability is degraded due to detection delays
Solution Approach 1:
The LDO regulator incorporates preliminary action by predicting voltage changes based on load current variations and proactively adjusting the output voltage before actual droop occurs. The controller detects changes in load current and preemptively modifies the control signal to the power transistors, compensating for detection delays and maintaining stability while operating at high speed.
Solution Approach 2:
The patent implements feedback mechanisms where the LDO core continuously monitors output voltage and load current conditions, and the controller adjusts the control signal based on this feedback. This closed-loop control enables the system to maintain stability by correcting voltage deviations in real-time, allowing high-speed operation without sacrificing output voltage stability.
Data Source
AI summary
A digital low-dropout (LDO) regulator may include: an LDO core configured to select a control mode based on a state of an output voltage of the digital LDO regulator provided to a load block and to output a control code based on the control mode; and a plurality of power transistors configured to control supply current supplied to the load block based on the control code. The control mode may include a first mode and a second mode for changing the supply current faster than in the first mode. The LDO core may be configured to perform a step-back operation to re-output a previous control code output at least one cycle ago and operate in the first mode based on the state of the output voltage corresponding to the first mode being detected while operating in the second mode.