Digital Lithography Pattern File Optimization
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Solution Overview
Problem
Conventional lithography methods are time-consuming and costly due to the process of transferring design patterns onto photomasks and verifying their accuracy, while digital lithography's verification and optimization processes are also processing intensive.
Innovation Solution
A method for optimizing digital pattern files for digital lithography devices involves removing redundant cells, reducing vertexes in arcs, replacing cells with alternative versions, and converting polygons to quad polygons, with each step involving comparisons to detect and correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography methods are used to transfer design patterns onto photomasks and verify accuracy, then manufacturing precision is improved, but loss of time and cost increase
Solution Approach 1:
The patent uses digital copying to replace physical photomask fabrication. Design patterns are digitized directly and transferred electronically to the digital lithography device, eliminating the need to create physical photomask copies. This digital copying process maintains manufacturing precision while dramatically reducing the time and cost associated with physical photomask production and verification
Solution Approach 2:
The patent replaces the mechanical photomask fabrication and verification system with a digital processing system. Instead of physically creating and examining photomasks, the system uses digital pattern files that are processed computationally, substituting mechanical operations with digital/ computational operations that are faster and more efficient
2Manufacturing precision
If digital lithography verification and optimization processes are applied, then manufacturing precision is improved, but use of energy and processing resources increase
Solution Approach 1:
The patent segments the optimization process into distinct sequential steps: removing redundant cells, reducing arc vertexes, replacing cells with alternative versions, and converting polygons to quad polygons. Each step performs a specific optimization function and compares results independently. This segmentation allows the system to process design patterns in manageable stages, reducing the computational energy required compared to a monolithic optimization process
Solution Approach 2:
The patent applies partial optimization actions at each step rather than attempting complete optimization all at once. Each optimization step performs a specific partial transformation (e.g., only removing redundant cells, then only reducing arc vertexes), and the results are compared and validated at each stage. This approach reduces processing energy by breaking down the complex optimization task into smaller, less computationally intensive partial actions
3Manufacturing precision
If multiple optimization steps are applied to digital pattern files, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the optimization process into four distinct segmented steps: (1) removing redundant cells, (2) reducing arc vertexes, (3) replacing cells with alternative versions, and (4) converting polygons to quad polygons. Each step is a separate, well-defined operation with clear input and output. This segmentation makes the complex optimization process more manageable and easier to implement, reducing perceived device complexity while maintaining manufacturing precision
Solution Approach 2:
The patent performs preliminary comparisons at each optimization step to validate results before proceeding to the next step. Each optimization action is followed by a comparison operation that checks the results against the previous state. This preliminary validation approach ensures that each step contributes meaningfully to the final optimized design, preventing unnecessary complexity from accumulating in the processing system
Data Source
AI summary
A digital pattern generation system comprises a memory and a controller. The controller is coupled the memory and is configured to remove redundant cells from a digital pattern file, generate a first updated digital pattern file and compare the first updated digital pattern file with the digital pattern file. Further a number of vertexes of a first arc of the first updated digital pattern file is reduced to generate a second updated digital pattern file. Additionally, a first cell of the second updated digital pattern file is replaced with an alternative version of the first cell to generate a third updated digital pattern file. Further, one or more polygons within the third updated digital pattern file is converted to one or more quad polygons to generate an optimized digital pattern file.


