Digital Lithography Via Alignment for IC Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving precise alignment and connection between vias and redistributed metal layers (RDLs) during semiconductor packaging, leading to misalignment and reduced integration density due to iterative reduction of feature sizes.
Innovation Solution
A method involving comparison of via positions and locations to generate position data, which is used to update and project RDL and connection via mask patterns with a digital lithography device, ensuring accurate alignment and patterning of vias and RDLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If iterative reduction of feature size is used to improve integration density, then more components can be integrated into a given area, but alignment precision between vias and RDLs deteriorates
Solution Approach 1:
The system performs preliminary measurement of actual via positions before RDL patterning, then uses this information to pre-correct the lithography mask pattern. This preliminary action compensates for alignment errors before the actual RDL formation process, ensuring precise alignment even as feature sizes are reduced to increase integration density.
Solution Approach 2:
The system implements a feedback loop where actual via positions are measured, compared to target positions, and the deviation information is fed back to dynamically adjust the lithography mask pattern. This closed-loop feedback ensures that RDLs align precisely with vias despite manufacturing variations and feature size reductions.
2Manufacturing precision
If dynamic adjustment of lithography mask pattern is implemented to improve alignment precision, then via-RDL alignment improves, but system complexity increases
Solution Approach 1:
The system introduces an intermediary computational layer that processes via position data and generates corrected mask patterns. This intermediary software application acts as a mediator between measurement data and lithography execution, simplifying the overall system architecture while achieving high alignment precision through data-driven mask adjustments.
Solution Approach 2:
The system creates a digital copy or model of the via positions and uses this virtual representation to generate corrected mask patterns computationally. This copying approach allows complex adjustments to be made in the digital domain before physical lithography, reducing the complexity of the physical lithography system while maintaining high alignment precision.
3Reliability
If new via positions are determined through comparison to improve alignment, then connection accuracy improves, but measurement and detection difficulty increases
Solution Approach 1:
The system employs a multi-functional measurement and processing platform that can handle various via position measurement tasks and automatically perform the comparison and correction operations. This universal system reduces the difficulty of measurement by integrating multiple functions into a single automated workflow, improving connection accuracy without proportionally increasing measurement complexity.
Data Source
AI summary
Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.