Digital Lock Detection in Phase and Delay Control Loops
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Solution Overview
Problem
Existing phase and delay locked loops face challenges in determining their locked state due to the limitations of analog and digital approaches, which are either not applicable or increase circuit complexity, especially in delay-locked loops where frequency of the feedback clock signal remains constant.
Innovation Solution
A lock detector is introduced that uses two digital control signals, an AND gate, an OR gate, a delay unit, and a processing circuit with a clock edge-triggered flip-flop to generate a status signal indicating the locked or unlocked state of the loop, independent of the duty cycle of the reference and feedback clock signals, with low circuit complexity and improved reproducibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog approaches are used to measure the change in control voltage to determine locked state, then the measurement can be performed, but the approach is not easily applicable to delay-locked loops and increases circuit complexity
Solution Approach 1:
The patent replaces analog voltage measurement methods with a digital logic-based detection system. Instead of measuring analog control voltage changes, the invention uses digital control signals from the charge pump combined with logic gates (AND, OR) and a delay unit to generate a lock status signal, thereby substituting mechanical/analog measurement with digital logic operations
Solution Approach 2:
The patent introduces an intermediary digital detection system that processes digital control signals through logic gates and delay units. This intermediary system acts as a mediator between the charge pump outputs and the lock status determination, avoiding direct analog measurement while providing clear digital lock detection
2Measurement precision
If digital approaches evaluate phase error by comparing meter readings, then the locked state can be determined, but this method cannot be used for delay-locked loops where feedback clock frequency remains constant
Solution Approach 1:
The patent creates a universal lock detection method that works for both phase-locked loops and delay-locked loops. By using digital control signals from the charge pump as the detection basis rather than phase error comparison or analog voltage measurement, the system achieves multi-functionality and can be applied to different types of locked loops regardless of their specific operating characteristics
3Measurement precision
If internal states of voltage-controlled delay chain are evaluated to determine lock status, then delay-locked loops can be monitored, but the corresponding circuits become very large
Solution Approach 1:
The patent extracts only the essential information needed for lock detection by using the digital control signals from the charge pump, rather than evaluating the entire internal state of the delay chain. This extraction approach obtains sufficient lock status information while avoiding the complexity of monitoring all delay chain elements
Data Source
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AI summary
The present invention relates to a lock detector (100) for monitoring a phase or delay control loop with a charge pump controlled by two digital control signals (S1, S2). The lock detector (100) comprises a processing circuit (50) configured to receive an AND gate (U1) of the two control signals (S1, S2) and a delayed variant (OV1) of an OR gate (O1) of the two control signals (S1, S2), and to generate a digital status signal (L1) from the received signals and output it via an output (35) of the lock detector (100). The status signal (L1) assumes a first value when the phase or delay control loop is locked and a second value different from the first value when the phase or delay control loop is unlocked.