Digital Loop Filter Architecture for Low-Latency Clock Data Recovery
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Solution Overview
Problem
High-speed data transmission systems face challenges in maintaining low latency and high jitter tolerance due to the limitations of existing clock data recovery circuits, which affect data transfer rates and bit error rates.
Innovation Solution
A clock data recovery circuit incorporating a digital loop filter with a proportional path and an integral path, utilizing sigma delta modulation arithmetic blocks and an integrator, to filter input jitter and generate a clock signal with improved phase interpolation, thereby reducing latency and enhancing jitter tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If existing clock data recovery circuits are used, then data transmission can be performed, but latency is high and jitter tolerance is low
Solution Approach 1:
The digital loop filter is divided into a proportional path and an integral path, each processing phase error signals through different computational sequences. The proportional path uses a first SDM arithmetic block with first SDM coefficient, while the integral path uses a second SDM arithmetic block with second SDM coefficient, allowing independent optimization of each path's latency and jitter tolerance characteristics
Solution Approach 2:
The patent applies sigma delta modulation with different SDM coefficients in the proportional and integral paths to transform the phase error signal. By changing the modulation parameters and coefficient values, the system achieves reduced latency while maintaining high jitter tolerance through optimized signal transformation
2Productivity
If high-speed data transmission is implemented, then data transfer rate increases, but jitter tolerance decreases
Solution Approach 1:
The digital loop filter continuously receives phase error signals from the phase detector and generates corrected clock signals through the proportional and integral paths. This closed-loop feedback mechanism dynamically adjusts the clock signal to compensate for jitter, enabling high-speed data transmission while maintaining high jitter tolerance through real-time error correction
3Reliability
If conventional digital loop filter structure is used, then filtering can be performed, but operation complexity and latency are high
Solution Approach 1:
The filtering operation is segmented into proportional filtering (first SDM arithmetic block) and integral filtering (second SDM arithmetic block with integrator). Each segment processes specific components of the phase error signal independently, reducing overall operation latency while maintaining comprehensive filtering performance through coordinated operation of both paths
Data Source
AI summary
A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.