Digital Loop Filter for Low-Latency Clock Data Recovery

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing clock data recovery circuits suffer from high latency and reduced jitter tolerance, which affects data transmission quality, especially in high-speed serial communication systems.

Innovation Solution

A digital loop filter with reduced latency and operations is integrated into the clock data recovery circuit, utilizing a proportional and integral path design with optimized arithmetic blocks to minimize latency and enhance jitter tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a conventional digital loop filter is used in the clock data recovery circuit, then the circuit can perform phase detection and correction, but the latency is high and jitter tolerance is reduced

Engineering Contradiction:

ImprovelatencyVSAvoidjitter tolerance

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The digital loop filter is segmented into separate proportional path and integral path components, each processing phase error signals through dedicated arithmetic blocks. This segmentation allows independent optimization of each path's latency characteristics while maintaining overall filter functionality and jitter tolerance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The loop filter employs dynamic coefficient adjustment where the proportional coefficient Kp and integral coefficient Ki are adaptively modified based on operating conditions. This dynamic adaptation enables the filter to optimize its response characteristics, reducing latency during transient states while maintaining stability for jitter suppression during steady-state operation.

Inventive Principle:

Principle #15Dynamics

2Measurement precision

If arithmetic operations are performed in the digital loop filter to achieve phase correction, then phase accuracy is improved, but the number of operations increases causing higher latency

Engineering Contradiction:

Improvephase accuracyVSAvoidlatency

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The filter applies partial correction actions through separate proportional and integral paths rather than performing complete correction through a single complex operation. The proportional path provides immediate partial correction while the integral path provides gradual additional correction, reducing overall latency while achieving accurate phase alignment.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The arithmetic operations use variable coefficients Kp and Ki that change based on the phase error magnitude and system state. By dynamically adjusting these parameters, the filter achieves high precision phase correction when needed while reducing operation intensity during normal operation, thereby minimizing latency.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentEP4181454B1Digital loop filter of low latency and less operation and clock data recovery circuit including the same

Publication Date: 2025.09.10 SAMSUNG ELECTRONICS CO LTD

Figure 1
Figure 2
Figure 3

AI summary

A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.