Digital Loop Filter Retiming for Repeated ADPLL Bandwidth Shifts
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Solution Overview
Problem
All-digital phase locked loop (ADPLL) systems in wireless communication devices face challenges in maintaining lock when switching loop bandwidths, leading to disturbances in ongoing communications due to the need for 'gear shifting' in loop gain changes.
Innovation Solution
A digital loop filter with flip-flops to store output values ensures continuity during amplification changes, allowing for multiple loop gain changes without losing lock, and using a feedback loop to stabilize the ADPLL by overwriting old loop gain values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If loop bandwidth is increased at the start to enable faster locking, then locking speed is improved, but phase noise signals outside the channel bandwidth increase
Solution Approach 1:
The system dynamically adjusts the loop bandwidth by switching between a first amplification parameter (higher bandwidth) during acquisition and a second amplification parameter (lower bandwidth) during tracking. This dynamic adjustment allows the ADPLL to achieve fast initial locking while maintaining low phase noise in the final tracked state.
2Object-generated harmful factors
If loop bandwidth is reduced once locked to reduce phase noise, then phase noise signals are reduced, but locking speed decreases
Solution Approach 1:
The system uses dynamic adjustment by switching between different amplification parameters based on the operational phase. During acquisition, a higher bandwidth parameter enables fast locking; during tracking, a lower bandwidth parameter reduces phase noise. This temporal separation of bandwidth requirements resolves the contradiction.
3Adaptability or versatility
If loop gain is changed (gear shifting) to adjust bandwidth, then bandwidth switching capability is improved, but lock stability is disturbed
Solution Approach 1:
The system prepares the second amplification parameter in advance within the digital loop filter's memory structure before it is needed. When switching from the first to the second parameter, the transition is smooth and pre-coordinated, preventing disturbance to the locked state. The digital loop filter is designed to accommodate parameter changes without disrupting the phase lock.
4Adaptability or versatility
If multiple bandwidth switches are performed, then adaptability is improved, but system complexity increases
Solution Approach 1:
The system implements unlimited bandwidth switching capability through a dynamic digital loop filter structure that can store and switch between multiple amplification parameters. The architecture uses flip-flops and multiplexers to enable rapid parameter changes without proportional increases in overall system complexity, allowing adaptive bandwidth adjustment for different communication scenarios.
Data Source
AI summary
This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.