Digital Frequency-Locked Loop for Two-Cycle Clock Locking
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Solution Overview
Problem
Existing systems for clock synthesis or data timing recovery in Phase Locked Loops (PLLs) require a transient time for locking, which cannot be completely skipped, limiting their rapidity and efficiency in achieving frequency accuracy and phase noise reduction.
Innovation Solution
A fully digital Frequency Locked Loop (FLL) system operating in the discrete time domain, utilizing a Digital Controlled Oscillator and integrator feedback, allows for the multiplication of the input frequency clock by an arbitrary factor without analog oscillators, ensuring convergence within two reference clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional Phase Locked Loop (PLL) with analog VCO is used for clock synthesis, then frequency multiplication can be achieved, but a transient locking time is required which limits rapidity and efficiency
Solution Approach 1:
The patent replaces the analog continuous-time oscillator (VCO) with a fully digital discrete-time oscillator implementation. The analog voltage-controlled oscillator is substituted with a digital counter and frequency divider system that operates in discrete time domains, eliminating the need for analog components and their associated transient locking behavior.
Solution Approach 2:
The patent changes the fundamental operating parameters from continuous analog domain to discrete digital domain. By transforming the oscillator from an analog VCO with continuous frequency control to a digital system with discrete frequency steps controlled by division ratios, the system achieves instantaneous frequency switching without transient locking time.
2Loss of time
If a fully digital Frequency Locked Loop system is used for clock synthesis, then transient locking time is eliminated and rapid convergence is achieved, but the system complexity increases compared to conventional analog PLL
Solution Approach 1:
The patent extracts and removes the analog VCO component from the traditional PLL architecture, replacing it with purely digital components. By taking out the complex analog continuous-time oscillator and its associated filtering requirements, the system simplifies the overall design while achieving faster locking through digital discrete-time operation.
Solution Approach 2:
The patent creates a digital copy of the oscillator function using discrete-time digital logic components (counters, frequency dividers) that replicate the frequency generation capability of the analog VCO without requiring analog circuitry. This digital copying approach eliminates transient locking while maintaining frequency synthesis functionality.
Data Source
AI summary
Embodiments of the present invention relate to a system for clock synthesis or data timing recovery. No analog continuous time oscillator is required, all the building blocks of a Frequency Locked Loop/Phase Locked Loop belonging in the digital discrete time domain. From a system-level perspective, the system is characterized by its strong non-linear behavior due to the intrinsic nature of some building blocks. This inherent non-linearity is responsible for some unusual, attractive property of the complete system. The system is able to multiply the input frequency clock by an arbitrarily large factor, ensuring in any case the convergence of the algorithm in two reference clock cycles.