Digital Memory Bit-Level Write Operation for Error Correction
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Solution Overview
Problem
As memory cell density increases in digital memory devices, soft errors such as bit flips due to random events become more likely, leading to increased power consumption and latency in error correction processes, where entire data words are written back during Read Modify Write cycles, even for single bit errors across multiple memory devices.
Innovation Solution
Implementing a controller that performs write operations at a granularity level less than a data word, allowing for serial or parallel access of bits, and precharging bit lines only for the specific bits to be written, thereby reducing power consumption and latency by writing corrected bits during idle times or scheduled operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction schemes are implemented to detect and correct soft errors, then reliability is improved, but power consumption and latency increase due to writing entire data words back during Read Modify Write cycles
Solution Approach 1:
The patent segments the data word into individual bits or groups of bits, allowing error correction to be applied at a finer granularity. Instead of correcting entire data words, the system identifies and corrects only the specific bits that contain errors, thereby reducing the amount of data that needs to be written back to memory and reducing power consumption.
Solution Approach 2:
The patent applies local quality by treating different bits of the data word differently based on their error status. Bits that are confirmed to be error-free are not subjected to write operations, while only the erroneous bits are corrected and written back. This localized approach minimizes unnecessary power consumption associated with writing entire data words.
2Reliability
If error correction schemes are implemented to detect and correct soft errors, then reliability is improved, but latency increases due to accessing multiple memory devices and precharging bit lines
Solution Approach 1:
The patent segments the error correction process into identifying only the specific bits that require correction. By determining the exact location of erroneous bits rather than treating entire data words uniformly, the system reduces the scope of memory access operations needed, thereby reducing latency.
Solution Approach 2:
The patent applies partial action by performing error correction only on the necessary bits rather than on entire data words. This partial correction approach reduces the number of memory access operations and precharging events, thereby reducing latency while still achieving the required error correction.
3Reliability
If entire data words are written back during Read Modify Write cycles, then error correction is ensured, but power consumption increases due to precharging bit lines for all bits
Solution Approach 1:
The patent segments the write operation to apply only to the specific bits that contain errors rather than to entire data words. This segmentation allows the system to avoid precharging bit lines for bits that do not require correction, thereby reducing power consumption while maintaining error correction effectiveness.
Solution Approach 2:
The patent applies local quality by differentiating between bits that require correction and those that do not. Only the erroneous bits are subjected to write operations and associated precharging, while error-free bits are left untouched. This localized treatment minimizes energy loss.
4Productivity
If memory cell density is increased to improve storage capacity, then productivity is improved, but soft error susceptibility increases leading to more frequent error correction operations
Solution Approach 1:
The patent changes the parameter of error correction granularity from the data word level to the bit level. This parameter change allows the system to handle soft errors more efficiently by correcting only the affected bits rather than entire data words, thereby mitigating the increased error susceptibility that comes with higher memory cell density.
Data Source
AI summary
Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the determining and the writing may be performed at a granularity level finer than a data word. In embodiments, the bit to be written may be determined by error correction.