Digital Microphone Dual-Edge Output on a Shared Data Line

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Solution Overview

Problem

Existing digital microphone systems face limitations in data output efficiency, particularly in multiplexed systems where microphones share a data line, leading to suboptimal data rates and dynamic range.

Innovation Solution

A digital microphone system that utilizes a periodic clock signal with dual phases to enable data output during both high and low phases, allowing microphones to transmit data during both halves of the clock cycle, thereby doubling the data rate and achieving a higher dynamic range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a digital microphone outputs one bit of data per clock cycle during a designated portion of the periodic clock signal in a multiplexed system, then multiple microphones can share a common data line, but the data output rate is limited and dynamic range is reduced

Engineering Contradiction:
Improvedata output rateVSAvoidmultiplexed system coordination
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies periodic action by utilizing both the rising edge and falling edge of the clock signal to output data bits. Instead of using only one edge (as in conventional multiplexed systems), the microphone outputs one bit during the rising edge portion and another bit during the falling edge portion of each clock cycle, effectively doubling the data output rate while maintaining periodic coordination in the multiplexed system.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the parameter of data output timing by utilizing both edges of the clock signal rather than just one. This parameter change allows the microphone to output two bits per clock cycle instead of one, thereby increasing the data output rate and improving dynamic range without requiring additional clock lines or increasing clock frequency.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the clock signal rate is increased to achieve higher data output rate, then more data can be transmitted, but power consumption increases

Engineering Contradiction:
Improvedata output rateVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements continuity of useful action by utilizing both the rising edge and falling edge of each clock cycle for data output. This continuous utilization of the clock signal throughout its entire period maximizes the data transmission efficiency at the given clock rate, eliminating wasted time when the microphone could be transmitting data, thereby achieving higher effective data rates without increasing clock frequency and power consumption.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If a dedicated data line is provided for each microphone, then each microphone can output data at full rate, but the system complexity and number of connections increase

Engineering Contradiction:
Improvedata output rate per microphoneVSAvoidnumber of data lines
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies merging by combining multiple microphones onto a single shared data line while maintaining full data output capability for each microphone. By utilizing both edges of the clock signal, each microphone can output two bits per clock cycle on the shared line, effectively merging multiple data streams without requiring dedicated data lines for each microphone, thus reducing system complexity while maintaining productivity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250373965A1Digital microphone data output
Publication Date: 2025.12.04 SENSIBEL AS
  • US20250373965A1 patent drawing
  • US20250373965A1 patent drawing
  • US20250373965A1 patent drawing

AI summary

A digital microphone system includes a digital microphone, a host circuit and an output data line. The host circuit is configured to provide a periodic clock signal to the digital microphone, wherein the periodic clock signal has a period comprising a first clock signal portion when the periodic clock signal is high and a second clock signal portion when the periodic clock signal is low. The digital microphone system is configured to cause the digital microphone to output acoustic signal data to the host circuit via the data line during the first and second clock signal portions.