Digital Modulation Circuit Without PLL for Simpler Synchronization
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Solution Overview
Problem
Conventional digital modulation methods for wireless communication, particularly in ultra-wideband systems, result in complex transmitter structures and high power consumption due to the use of phase locked loop (PLL) circuits, and complicate carrier signal synchronization in receivers.
Innovation Solution
A digital modulation circuit utilizing a clock generator, up/down counter, controller, and band-pass filter to generate and modulate transmission signals, eliminating the need for PLL circuits and simplifying synchronization, with the controller determining counting operations based on digital data and the band-pass filter converting the signal into a sine waveform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locked loop (PLL) circuit is used to fix the frequency of the local oscillating signal, then the frequency stability is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent extracts and removes the PLL circuit from the modulation system, replacing it with a direct digital modulation approach using a counter and waveform generator. This eliminates the complex frequency locking mechanism while maintaining the essential modulation function through direct generation of the modulated signal from a reference clock.
Solution Approach 2:
The patent replaces the analog PLL-based frequency control mechanism with a digital counting and waveform generation system. The counter generates digital signals based on clock cycles, and a waveform generator converts these to analog modulated signals, substituting mechanical/analog frequency control with digital logic operations.
2Reliability
If a phase locked loop (PLL) circuit is used to fix the frequency of the local oscillating signal, then the frequency stability is improved, but the power consumption increases
Solution Approach 1:
The patent extracts and removes the power-intensive PLL circuit from the transmitter, replacing it with a simpler digital counting system that consumes significantly less power while achieving the same frequency stabilization effect through digital reference clock generation.
3Productivity
If a conventional modulation method using local oscillation signal mixing is employed, then the communication bandwidth is controlled, but the carrier signal synchronization acquisition becomes complicated
Solution Approach 1:
The patent introduces a reference clock signal as an intermediary that serves dual purposes: it controls the modulation timing and provides the carrier frequency reference. This single reference signal replaces the separate local oscillation signal and synchronization reference, simplifying the receiver's synchronization acquisition by providing a direct timing and frequency reference.
Data Source
AI summary
Provided is a digital modulation circuit constructed with only a digital circuit. The digital modulation circuit includes: a clock generator which generates a reference clock pulse having a predetermined period; an up/down counter which generates a count value having predetermined bits by up-counting or down-counting the reference clock pulse and outputs a bit in the count value as a transmission signal; a controller which determines a counting start/end time point of the up/down counter and determine which one of the up-counting operation and the down-counting operation of the up/down counter is to be performed, according to a value of digital transmission data that is to be transmitted; and a band-pass filter which converts a waveform of the transmission signal output from the up/down counter into a sine waveform.