Digital Oscillator Pulse Modulation for Fine Frequency Stepping
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Solution Overview
Problem
Existing digitally controllable oscillators face challenges in achieving fine frequency stepping with high accuracy due to limitations in varactor resolution and complex calibration requirements, leading to high phase noise and spur issues in RF applications.
Innovation Solution
A digitally controllable oscillator design that incorporates a phase locked loop with a frequency divider, phase detector, and error signal pulse train modulator, allowing for pulse train modulation of the error signal to achieve precise frequency control without complex calibration, utilizing digital pulse train modulation to distribute pulses evenly within a time window for reduced noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If varactor resolution is increased to achieve finer frequency stepping, then frequency resolution is improved, but manufacturing precision and device complexity increase due to limitations in advanced CMOS lithography
Solution Approach 1:
The patent replaces the mechanical/analog varactor-based frequency control system with a digital pulse train modulation system. Instead of using analog capacitance variation through varactors, the invention uses digital pulses inserted into the reference clock signal to achieve frequency control. This substitution of digital for analog mechanisms enables finer frequency resolution without being constrained by varactor manufacturing limitations in CMOS lithography.
Solution Approach 2:
The patent changes the control parameter from analog capacitance (varactor) to digital pulse timing and position. By varying the insertion points and numbers of pulses within the reference clock period, the system achieves continuous frequency control with very fine resolution. This parameter transformation from analog to digital domain allows precision beyond what is physically achievable with analog varactor devices.
2Measurement precision
If Sigma-Delta Modulation techniques are used to improve frequency resolution, then frequency resolution is enhanced, but device complexity and calibration requirements increase
Solution Approach 1:
The patent extracts the frequency control function from the complex Sigma-Delta modulator architecture and implements it directly through pulse insertion logic in the reference clock path. By taking out the essential frequency control mechanism and simplifying it to pulse position and count modulation, the system achieves fine frequency resolution without requiring complex multi-stage noise shaping modulators, reducing device complexity significantly.
Solution Approach 2:
The patent uses a simplified copy of the reference clock signal, inserting digital pulses at specific positions within the clock period. Instead of implementing a full Sigma-Delta modulation architecture, the invention creates a simplified version that achieves the same frequency control objective through direct pulse insertion, eliminating the need for complex feedback loops and noise shaping circuits.
3Measurement precision
If complex capacitive divider structures are used to reduce quantization noise, then frequency resolution is improved, but device complexity and calibration algorithms increase
Solution Approach 1:
The patent replaces the complex analog capacitive divider structure with a digital pulse insertion mechanism. Instead of using multiple capacitors in complex configurations to achieve fine frequency steps, the invention uses digital logic to insert variable numbers of pulses into the reference clock, achieving the same frequency resolution effect purely in the digital domain without any analog capacitive matching requirements.
4Measurement precision
If fine frequency stepping is achieved through high-speed SD dithering, then frequency resolution is improved, but phase noise increases due to quantization noise
Solution Approach 1:
The patent uses periodic pulse insertion synchronized to the reference clock period. By inserting pulses at regular intervals and at specific positions within each clock period, the system achieves fine frequency resolution without random dithering. This periodic, deterministic approach avoids the quantization noise and phase noise associated with high-speed Sigma-Delta dithering, while still enabling very fine frequency steps through precise pulse positioning.
Data Source
AI summary
An oscillator is provided. The oscillator is configured for generating an output signal which is phase locked to an input signal. The oscillator comprises a controlled oscillator configured for generating the output signal based on an oscillator input signal. Moreover, the oscillator comprises a frequency divider configured for dividing the frequency of the output signal, resulting in a frequency divided feedback signal. Also, the oscillator comprises a phase detector, which is configured for generating an error signal based upon the frequency divided feedback signal and the input signal. Also, the oscillator comprises an error signal pulse train modulator configured for generating the oscillator input signal by performing a pulse train modulation of the error signal) or a signal derived from the error signal based on the input signal.