Digital Output Driver Using Thin-Oxide FETs for Cost-Effective Voltage Translation
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Solution Overview
Problem
There is a need for a digital output driver that can interface with higher I/O voltages using thin-oxide FETs to reduce manufacturing costs by avoiding the additional masks required for thick-oxide FETs, while maintaining performance and ensuring reliable voltage translation between core and pad supply voltages.
Innovation Solution
A digital output driver and input buffer design utilizing thin-oxide FETs, comprising a pre-driver and driver with a latch and latch driver, and including multiple N-FETs and P-FETs stacked together, with specific voltage ranges and gate control circuits to manage supply voltages and prevent voltage leakage, allowing for efficient level shifting and signal buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick-oxide FETs are used to interface with higher I/O voltages, then voltage handling capability is improved, but manufacturing cost increases due to additional masks
Solution Approach 1:
The patent changes the operating parameters of thin-oxide FETs by implementing a multi-stage voltage translation architecture. The pre-driver stage translates voltages from VCORE to VPAD, and the driver stage further translates to the external I/O voltage level. This parameter transformation allows thin-oxide FETs to handle higher voltages indirectly without requiring thick-oxide devices, thereby avoiding additional manufacturing masks while maintaining voltage handling capability
Solution Approach 2:
The patent introduces intermediate voltage translation stages (pre-driver and driver circuits) as mediators between the low-voltage thin-oxide FET core and the high-voltage external I/O interface. These intermediary circuits translate voltage levels progressively, allowing thin-oxide FETs to interface with higher voltages without direct exposure, thus eliminating the need for thick-oxide FETs and their associated additional masks
2Ease of manufacture
If thin-oxide FETs are used for I/O interfacing, then manufacturing cost is reduced by avoiding additional masks, but voltage handling capability deteriorates
Solution Approach 1:
The patent segments the voltage translation function into multiple independent stages: the pre-driver stage handles translation from VCORE to VPAD, while the driver stage handles translation to the external I/O voltage level. Each stage uses thin-oxide FETs operating within their safe voltage ranges, collectively achieving high-voltage interfacing capability without requiring any single thin-oxide FET to exceed its rating, thus maintaining both cost efficiency and voltage handling capability
Solution Approach 2:
The patent adds a temporal dimension to voltage handling by using controlled timing sequences in the multi-stage translation process. The pre-driver stage operates first to establish intermediate voltage levels, then the driver stage operates subsequently to achieve the final high voltage level. This sequential, time-based approach allows thin-oxide FETs to handle higher voltages indirectly through staged translation, maintaining manufacturing cost efficiency while achieving the required voltage handling capability
Data Source
AI summary
A digital output driver includes a pre-driver and a driver that may be implemented with thin-oxide FETs. The pre-driver generates first and second digital signals based on a digital input signal. The first digital signal has a first voltage range determined by a first (e.g., pad) supply voltage and an intermediate voltage. The second digital signal has a second voltage range determined by a second (e.g., core) supply voltage and circuit ground. The driver receives the first and second digital signals and provides a digital output signal having a third voltage range determined by the first supply voltage and circuit ground. The pre-driver may include a latch and a latch driver. The latch stores the current logic value for the digital input signal. The latch driver writes the logic value to the latch. The latch driver is enabled for a short time duration to write the logic value and is turned off afterward.