Digital PFC Control With DLPAC for High-Frequency Grids
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Solution Overview
Problem
Conventional power factor correction (PFC) designs are inadequate for high-frequency grids and high-power applications, such as those in aircraft, due to limitations in bandwidth and increased switching frequency, which leads to weight, size, and complexity issues, as well as stability and efficiency concerns.
Innovation Solution
The implementation of digital leading phase admittance cancellation (DLPAC) modifies the PFC input impedance to enhance stability and eliminate damping components, incorporating delay compensation to address the challenges of digital control systems, thereby reducing the weight and size of power converters while maintaining high power density and reliability across a wide range of frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PFC designs are used for high-frequency grids, then power factor correction is achieved, but switching frequency must be increased much higher than for 50-60 Hz applications, leading to increased switching losses
Solution Approach 1:
The patent applies LPAC (Leading phase admittance cancellation) which modifies the control parameters of the PFC circuit by introducing a third admittance component Y3(s) that cancels the phase lag effect of Y1(s). This parameter change in the control strategy allows the system to achieve effective power factor correction at lower switching frequencies, directly reducing switching losses while maintaining PFC performance in high-frequency grid applications
Solution Approach 2:
The patent replaces conventional multiplier-based control mechanisms with an admittance-based control approach. By substituting the traditional control method with an admittance cancellation strategy, the system achieves better PFC performance without requiring excessively high switching frequencies, thereby reducing switching losses in high-power and high-frequency applications
2Reliability
If bandwidth of PFC circuit is increased to pass all significant harmonics, then power factor correction improves, but switching frequency must be increased to maintain stability
Solution Approach 1:
The patent modifies the control parameters by implementing LPAC, which introduces a corrective admittance component that cancels phase lag. This parameter modification allows the PFC circuit to achieve the necessary bandwidth for harmonic filtering without proportionally increasing the switching frequency, thus maintaining stability while improving power factor correction performance
3Reliability
If switching frequency is increased to satisfy bandwidth criteria for high-frequency grids, then power factor correction bandwidth is sufficient, but switching losses increase significantly
Solution Approach 1:
The patent changes the control parameters by implementing admittance cancellation, where Y3(s) is designed to counteract the phase lag of Y1(s). This parameter change enables the system to achieve adequate bandwidth for power factor correction without requiring switching frequencies hundreds of times the fundamental frequency, thus significantly reducing switching losses in high-power applications
4Stability of the object's composition
If damping components are added to improve stability, then system stability improves, but weight, volume and temperature increase
Solution Approach 1:
The patent replaces physical damping components with a digital control-based admittance cancellation system. By substituting mechanical/passive damping elements with an active control strategy (DLPAC), the system achieves stability through software-based compensation rather than additional physical components, thereby reducing weight, volume, and thermal management requirements
5Reliability
If conventional PFC designs are used, then power factor correction works for low-frequency grids, but they are not suitable for high-frequency grids and high power applications
Solution Approach 1:
The patent changes the fundamental control parameters by implementing LPAC/DLPAC, which introduces an admittance cancellation mechanism that is specifically designed to handle high-frequency operation. This parameter change enables the PFC system to adapt to high-frequency grids (360 Hz to 800 Hz) and high-power applications, significantly expanding the frequency range adaptability compared to conventional designs
Data Source
AI summary
A power factor correction circuit comprising: a global voltage input; and means for deriving a reference current from the global voltage; whereby the means for deriving the reference current comprises a digital leading phase admittance cancellation, DLPAC, transfer function and a filter, whereby the reference current is derived from a sum of an output of the DLPAC transfer function and an output of the filter, and further comprising means for compensating for delays in the DLPAC function.