Digital Phase Frequency Detector for Accurate, Noise-Resistant PLL Locking
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Solution Overview
Problem
Conventional digital phase locked loops (PLLs) face challenges with low accuracy and high sensitivity to external noises due to their analog nature, and digital PLLs require a phase frequency detector (PFD) that is compact, fast, and accurate for phase and frequency detection.
Innovation Solution
A digital phase frequency detector (PFD) is designed with a detection unit, reset unit, and phase comparison unit using flip-flops and latch blocks to generate phase comparison signals, and a gain control unit to adjust gain based on phase differences, enabling precise phase and frequency detection and locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional analog PLL is used, then the circuit can be implemented with traditional components, but the accuracy is low and sensitivity to external noises is high
Solution Approach 1:
The patent replaces the analog mechanical/electrical system with a digital system. The phase frequency detector is implemented using digital logic circuits including flip-flops, latches, and logic gates that operate in the digital domain, thereby eliminating the sensitivity to external noises inherent in analog systems while improving measurement precision through digital signal processing
2Measurement precision
If a digital PFD is designed with multiple flip-flops and latch blocks for accurate phase comparison, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent segments the phase frequency detection function into distinct digital logic modules: detection units that generate edge signals, flip-flops that capture phase information, latch blocks that store comparison results, and logic gates that generate final output signals. This segmentation allows each component to perform a specific function with high precision while maintaining overall circuit manageability through modular architecture
Solution Approach 2:
The digital logic components in the patent serve multiple functions: the detection unit generates both reference and feedback edge signals, the flip-flops perform both phase sampling and signal synchronization, and the latch blocks provide both temporary storage and signal conditioning. This multi-functionality reduces the total number of components needed while maintaining high measurement precision
Data Source
AI summary
A digital phase frequency detector includes a detection unit, a reset unit and a phase comparison unit. The detection unit detects edges of a reference signal and a feedback input signal to generate a reference edge signal and a feedback edge signal. The reset unit generates a reset signal resetting the detection unit based upon the reference edge signal and the feedback edge signal. The phase comparison unit generates first and second phase comparison signals based upon the reference edge signal and the feedback edge signal. The phase comparison unit includes a first flip-flop generating a first comparison signal based upon the reference edge signal and the feedback edge signal, a second flip-flop generating a second comparison signal based upon the reference edge signal and the feedback edge signal, and a latch block latching the first and second comparison signals to generate the first and second phase comparison signals.