Digital Phase Aligner Using Parallel Delay Sampling
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Solution Overview
Problem
Existing phase alignment circuits in electronic circuits, such as PLLs and DLLs, rely on incremental adjustments and analog components, which can be area-intensive and slow, especially when aligning clock and data signals at high speeds.
Innovation Solution
A digital phase alignment circuit that captures and evaluates multiple samples of a signal in parallel, using a shift register and detection circuitry to select the appropriate delay element output, eliminating the need for analog components and feedback loops, thereby achieving rapid and precise signal alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If incremental adjustment circuits (PLL/DLL) are used for phase alignment, then phase alignment capability is achieved, but circuit area and adjustment time increase
Solution Approach 1:
The patent pre-generates all possible phase-aligned versions of the first signal through parallel delay paths before the alignment decision is made. This eliminates the need for incremental adjustment, as the correct aligned signal is already prepared and can be selected immediately when phase alignment is required.
Solution Approach 2:
The patent divides the phase alignment function into multiple parallel delay paths, each introducing a different predetermined delay. This segmentation allows simultaneous presentation of multiple phase options, replacing the sequential incremental adjustment approach with parallel independent paths that can be quickly selected.
2Reliability
If analog phase detector and feedback loop are used, then phase alignment is achieved, but circuit area increases
Solution Approach 1:
The patent replaces the analog phase detector and feedback loop mechanism with a digital selection mechanism. Instead of using analog components to detect and correct phase differences, the system uses digital logic to select from pre-generated phase-aligned signals, eliminating the need for complex analog circuitry.
Solution Approach 2:
The patent creates multiple copies of the input signal through parallel delay paths, each copy representing a different phase alignment state. This allows the system to work with copies rather than continuously adjusting the original signal, simplifying the alignment mechanism and reducing circuit area.
3Measurement precision
If incremental adjustments are made over time, then phase alignment is achieved, but alignment speed decreases
Solution Approach 1:
The patent pre-calculates and prepares all possible phase alignment configurations through parallel delay paths before they are needed. This eliminates the time required for incremental adjustments, as the correct aligned signal is already available for immediate selection, achieving both high precision and high speed.
Solution Approach 2:
The patent maintains continuous availability of all phase-aligned signal versions through parallel paths, rather than sequentially generating them through incremental adjustments. This continuous readiness of multiple options enables immediate selection and maintains high alignment speed without sacrificing precision.
Data Source
AI summary
A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal.