Digital Phase Detector With Adjustable Sampling Clock Resolution
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Solution Overview
Problem
Existing digital phase detectors face limitations in phase resolution due to the linearity of analog phase detectors and the resolution of analog-digital converters, as well as the speed of electronic components in sampling circuits, particularly when using a higher frequency sampling clock signal.
Innovation Solution
A digital phase detector generates a digitally adjustable auxiliary sampling clock signal with finer steps than the original sampling clock signal, allowing for increased phase resolution by sampling the input clock signal with this auxiliary signal and adjusting the phase displacement based on evaluation results to generate a more significant digital component of the phase detection signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a higher frequency sampling clock signal is used to improve phase resolution, then phase resolution is improved, but the speed of electronic components becomes a limiting factor
Solution Approach 1:
The phase detection process is divided into two independent paths: a high-speed path that provides coarse phase information and a high-resolution path that provides fine phase information. This segmentation allows each path to be optimized independently, resolving the contradiction between speed and precision.
Solution Approach 2:
A buffer register is introduced as an intermediary element to store the control signal generated by the high-resolution path. This buffer decouples the timing requirements of the two paths, allowing the high-resolution path to operate at higher frequencies without being constrained by the speed limitations of the sampling circuit.
2Measurement precision
If an analog phase detector with analog-digital converter is used, then phase detection capability is achieved, but phase resolution is limited by linearity and converter resolution
Solution Approach 1:
The patent replaces the analog phase detection mechanism with a fully digital approach. Instead of using an analog phase detector followed by an ADC, the invention uses digital logic circuits (XOR gate, buffer register, and phase displacement device) to perform phase detection entirely in the digital domain, eliminating the limitations of analog linearity and converter resolution.
3Measurement precision
If sampling circuit speed is increased to improve phase resolution, then phase resolution improves, but device complexity and component speed requirements increase
Solution Approach 1:
The sampling operation is segmented into two independent paths with different resolution requirements. The first path uses a simple sampling circuit for coarse detection, while the second path uses a buffer register and phase displacement device for fine detection. This segmentation reduces the complexity requirements of each individual component.
Solution Approach 2:
The invention introduces dynamic phase displacement of the sampling clock signal based on the control signal from the high-resolution path. This dynamic adjustment allows the system to achieve high phase resolution without requiring the entire sampling circuit to operate at extremely high speeds, as only the phase timing needs to be dynamically adjusted.
Data Source
AI summary
The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (14), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (14), but is subjected beforehand to a digitally adjustable phase displacement (12). There originates an “auxiliary sampling clock signal” (CK<1:8>). The sampling (14) delivers a first, more significant digital component (OUT1<9:0>) of the phase detection signal (PD_OUT). Based on an evaluation of this first digital component (OUT1<9:0>) a phase displacement (12) is undertaken and a second digital component (OUT2<12:0>) of the phase detection signal (PD_OUT) is generated. The auxiliary sampling clock signal (CK<1:8>) is here adjustable in steps, which in each case are smaller than one period of the sampling clock signal (CK).