Digital Phase-Frequency Detection for Stable PLL Convergence
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Solution Overview
Problem
Traditional phase-frequency detectors in phase-lock loop circuits face issues such as output signals being analog, time-varying error signals leading to inconstant frequency change rates, and over-control problems causing oscillations, which hinder fast convergence and stability.
Innovation Solution
A digital phase-frequency detector with a state machine maintaining UP, DOWN, and IDLE states, recording transition times to generate digital control signals and using UP and DOWN gain counters for constant gain control, enabling fast convergence and reducing over-control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a typical phase-frequency detector is used in a charge pump PLL, then the frequency and phase error can be detected, but the error signal becomes time-varying resulting in inconstant frequency change rate during VCO tuning
Solution Approach 1:
The patent applies preliminary action by pre-defining discrete phase regions (first phase region and second phase region) and their corresponding frequency change rates before the actual phase-frequency detection occurs. The state machine is pre-configured with transition rules between states based on these predefined regions, allowing the system to immediately apply the appropriate frequency change rate when a phase error is detected, rather than calculating or adjusting it dynamically. This eliminates the time-varying nature of the error signal and ensures constant frequency change rates during VCO tuning.
2Speed
If a typical phase-frequency detector generates UP or DOWN signals to control VCO frequency, then frequency adjustment is achieved, but over-control occurs causing the feedback clock to oscillate around the reference clock
Solution Approach 1:
The patent applies parameter changes by introducing a state machine with discrete states (first state, second state, third state) that changes based on the detected phase error magnitude and direction. Instead of continuously adjusting the VCO frequency with analog UP/DOWN signals that can cause over-control, the system transitions between defined states with specific frequency change rates. The frequency change rate parameter is modified based on the current state and the detected phase error, allowing fast convergence while preventing oscillation by selecting appropriate discrete frequency adjustment levels.
Solution Approach 2:
The patent applies dynamics by implementing a dynamic state machine that adapts its behavior based on real-time phase error detection. The state machine dynamically transitions between states (first, second, third states) depending on whether the phase error falls in the first or second phase region, and whether the reference clock frequency is higher or lower than the feedback clock frequency. This dynamic state transitions enable the system to achieve fast frequency adjustment while maintaining stability by selecting appropriate frequency change rates for each state condition.
3Ease of operation
If analog output control signals are used from the phase-frequency detector, then continuous control is achieved, but the signals cannot be used in all-digital PLLs
Solution Approach 1:
The patent applies mechanics substitution by replacing the analog output control signal mechanism with a digital state machine output mechanism. Instead of generating continuous analog UP/DOWN signals that are incompatible with all-digital PLLs, the system uses a digital state machine that outputs digital control signals representing different frequency change rates. The phase-frequency detector's output is converted from analog to digital domain through the state machine, which processes the phase error information and generates digital control words that can directly interface with digital frequency synthesizers and all-digital PLL components.
Data Source
AI summary
The present invention relates to a method and device for phase-frequency detection in a phase-lock loop circuit. The method comprises receiving compare edge of a reference clock signal and compare edge of a feedback clock signal, maintaining a phase/frequency detector, PFD, state machine with three PFD states, UP, DOWN, and IDLE, based on the received compare edges of the reference and feedback clock signals, recording current and previous time the state machine stays in UP or DOWN states, generating an UP or DOWN signal based on transition of PFD states and the comparison between recorded current time and recorded previous time; and outputting a digital control signal to a feedback frequency control device based on the UP or DOWN signal. A device and system is arranged to execute the method according to the present invention.