Digital Phase Interpolator With Half-Weight Auxiliary Units

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Solution Overview

Problem

Traditional high-bit digital phase interpolators experience significant increases in power consumption and area due to the multiplication of basic interpolating units as the number of interpolation bits increases.

Innovation Solution

The digital phase interpolator incorporates a configuration with a first and second phase interpolating unit, each connected in parallel with a corresponding auxiliary interpolating unit, and a buffer unit, where the auxiliary units have half the weight of the basic interpolating units, allowing for reduced power consumption and area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of interpolation bits increases to achieve high-bit digital phase interpolation, then the interpolation precision is improved, but the number of basic interpolating units multiplies resulting in significant increase in power consumption and area

Engineering Contradiction:
Improveinterpolation precisionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent divides the high-bit phase interpolator into multiple N-bit phase interpolating units (first, second, third, and fourth units) that process different bit segments of the interpolation signal. Each unit handles a subset of the total interpolation bits, allowing the system to achieve high-bit precision without requiring a single large array of basic interpolating units. This segmentation reduces the number of units needed in each parallel path while maintaining overall precision.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If the number of interpolation bits increases to achieve high-bit digital phase interpolation, then the interpolation precision is improved, but the area occupation increases significantly

Engineering Contradiction:
Improveinterpolation precisionVSAvoidarea occupation
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent segments the phase interpolation task across multiple N-bit units (first, second, third, and fourth phase interpolating units) that each handle a portion of the total bits. This segmentation allows the system to achieve high-bit precision while keeping the area of each individual unit manageable, as each unit only needs to implement N basic interpolating units rather than the full high-bit count.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension by using different delay amounts for different bit segments. The first and second phase interpolating units process lower-bit segments with one delay amount, while the third and fourth units process higher-bit segments with a different delay amount. This dimensional approach allows efficient resource utilization across time and space, reducing overall area occupation while maintaining precision.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If traditional N-bit digital phase interpolator uses N basic interpolating units connected directly for interpolation, then the implementation is simple, but the device complexity increases significantly for high-bit interpolation

Engineering Contradiction:
Improveimplementation simplicityVSAvoiddevice complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent divides the high-bit phase interpolator into multiple N-bit phase interpolating units (first, second, third, and fourth units) that process different bit segments. Each unit maintains the simple N-bit structure with N basic interpolating units, preserving implementation simplicity at the unit level while achieving high-bit functionality through their coordinated operation with different delay amounts.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250192764A1Digital phase interpolator
Publication Date: 2025.06.12 MONTAGE ELECTRONICS (SHANGHAI) CO LTD
  • US20250192764A1 patent drawing
  • US20250192764A1 patent drawing
  • US20250192764A1 patent drawing

AI summary

A digital phase interpolator includes: first and second phase interpolating units, first and second auxiliary interpolating units, and a buffer unit. The first auxiliary interpolating unit is connected with the first phase interpolating unit between a first input signal and an input end of the buffer unit. The second auxiliary interpolating unit is connected with the second phase interpolating unit between a second input signal and the input end of the buffer unit, and there is a preset phase difference between the first input signal and the second input signal. An output end of the buffer unit is an output end of the digital phase interpolator. Both the first and second phase interpolating units have N basic interpolating units connected in parallel, and weights of the first and second auxiliary interpolating units are both half of the weight of the basic interpolating unit, wherein N is greater than 1.