Digital Phase Detector Using Integer and Fraction Phase Paths
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Solution Overview
Problem
Conventional digital phase locked loops face challenges with high power consumption and large size due to the use of large digital frequency detectors, which also result in low accuracy and sensitivity to external noises.
Innovation Solution
A digital phase detector and digital phase locked loop design that includes a quantization unit, conversion units, and a calculation unit to accurately detect phase differences between reference and oscillation signals, implemented in a compact structure to minimize size and power consumption, using ring oscillators, latch blocks, and counter blocks to generate and convert phase information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large size digital frequency detector is used to accurately detect phase difference, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The phase detection function is segmented into two independent paths: an integer phase detection path using a simple counter to detect whole cycle differences, and a fraction phase detection path using a timing unit to detect sub-cycle phase differences. This segmentation allows accurate phase measurement without requiring a large complex detector, as each segment handles a specific aspect of phase detection with minimal complexity.
Solution Approach 2:
A timing unit is introduced as an intermediary component to measure the time difference between rising edges of reference and oscillation signals. This timing unit acts as a mediator that converts complex phase relationship analysis into simple time interval measurement, enabling accurate fraction phase detection without requiring a large frequency detector.
2Measurement precision
If a large size digital frequency detector is used to accurately detect phase difference, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The power consumption is reduced by segmenting the detection function into simple counting operations for integer phase and timing measurements for fraction phase. Each segment uses minimal computational resources, avoiding the high power consumption associated with large complex frequency detectors while maintaining accurate phase measurement capability.
Solution Approach 2:
The invention uses simple, low-cost components such as counters and timing units that consume minimal power, replacing the expensive (in terms of power consumption) large frequency detector. These simple components perform their specific detection functions efficiently and are discarded in favor of the combined approach.
3Device complexity
If conventional analog circuits are used for phase locked loop, then device complexity is reduced, but measurement precision and noise immunity deteriorate
Solution Approach 1:
The invention replaces the mechanical/analog circuit approach with a digital system that uses counting and timing operations. The analog phase-frequency detector and charge pump are substituted with digital counters, timing units, and adders that perform phase measurement through digital signal processing, eliminating noise sensitivity while maintaining simplicity.
Solution Approach 2:
The invention changes the operating parameters from continuous analog voltages to discrete digital counts and time measurements. By converting the phase detection problem into digital domain with defined counting periods and timing intervals, the system achieves noise immunity and high precision without complex analog circuitry.
Data Source
AI summary
A digital phase detector includes a quantization unit that quantizes a frequency of a reference signal to generate reference delay information and reference integer phase information, and quantizes a frequency of an oscillation signal to generate oscillation delay information and oscillation integer phase information. A first conversion unit converts the frequency of the reference signal into reference frequency information based upon the reference delay information and the reference integer phase information. A second conversion unit converts the frequency of the oscillation signal into oscillation frequency information based upon the oscillation delay information and the oscillation integer phase information. A calculation unit converts the reference frequency information and the oscillation frequency information into first and second phase information, respectively, and outputs a digital phase difference between the first phase information and the second phase information.


