Digital Phase Locked Loops for Packet Stream Rate Matching
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Solution Overview
Problem
The variation in packet transmission time between a digital source device and a sink device, especially when packet streams are multiplexed, makes it difficult for the sink device to synchronize with the source clock frequency, leading to issues like improper decoding or loss of picture.
Innovation Solution
A system that includes a timestamp estimator, filters, and a scheduler to generate and update estimates of the source clock frequency, using error calculations and filtering to minimize frequency variations and ensure accurate timestamping of packets, thereby stabilizing the clock synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packet streams are multiplexed onto the same channel to increase transmission efficiency, then productivity is improved, but the variation in packet transmission time increases, making it difficult for the sink device to synchronize with the source clock frequency
Solution Approach 1:
The patent implements a feedback mechanism where the sink device calculates timestamp errors based on received PCR timestamps and local clock timestamps, then uses these errors to adjust the local clock frequency through a phase-locked loop. This closed-loop feedback enables the sink device to dynamically track and synchronize with the source clock frequency despite variations introduced by multiplexing.
Solution Approach 2:
The patent introduces PCR timestamps as an intermediary carrier that conveys source clock information through the multiplexed packet stream. These timestamps serve as a mediator between the source and sink devices, allowing the sink to extract and use source clock references even when packets experience variable transmission delays due to multiplexing.
2Measurement precision
If the sink device attempts to lock onto the source clock frequency with high precision, then measurement precision is improved, but the complexity of the synchronization system increases
Solution Approach 1:
The patent enables the sink device to perform self-service synchronization by autonomously calculating timestamp errors, filtering these errors, and adjusting its own local clock frequency without requiring complex external synchronization infrastructure. The sink device uses its own resources to achieve and maintain lock with the source clock.
Solution Approach 2:
The patent employs parameter changes in the form of adjustable filter coefficients and frequency update step sizes within the phase-locked loop. These parameters can be tuned to balance between locking speed and stability, allowing the system to achieve high measurement precision while controlling complexity through configurable parameters rather than fixed complex architecture.
Data Source
AI summary
A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.