Digital Phase Rotator for Residual RF Phase Noise Compensation
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Solution Overview
Problem
Phase noise or phase jitter in Radio Frequency (RF) communications systems significantly affects performance by causing misread data bits and increasing noise levels, and existing phase noise control methods, such as Analog Phase Lock Loops (APLLs) and Digital Phase Lock Loops (DPLLs), are suboptimal due to causality and stability issues.
Innovation Solution
An All Digital Phase Locked Loop (ADPLL) with a Phase Noise Canceler (PNC) that uses digital phase error metric samples to rotate the phase of data signals and compensate for residual phase noise, employing a digital loop filter and a phase rotator to minimize phase errors, and optionally includes adaptive filters for smoothening phase error values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Analog Phase Lock Loops (APLLs) or Digital Phase Lock Loops (DPLLs) are used for phase noise control, then phase noise mitigation is achieved, but the system performance is limited due to causality and stability issues
Solution Approach 1:
The patent segments the phase noise control function into two independent parts: the DPLL handles coarse phase locking while the PNC handles fine phase error compensation. This segmentation allows each component to operate optimally without the stability and causality constraints that limit traditional unified PLL structures.
Solution Approach 2:
The patent introduces a phase rotator as an intermediary component between the DPLL and the data signal path. This phase rotator uses the phase error metric from the DPLL to pre-compensate the data signal, acting as a mediator that transfers phase correction information without introducing the stability issues inherent in traditional feedback loops.
2Reliability
If phase lock loop is used for phase noise control, then phase noise mitigation is achieved, but causality and delay in the loop limit performance
Solution Approach 1:
The patent applies preliminary action by using the phase error metric from the DPLL to pre-rotate the data signal before transmission. This pre-compensation occurs in advance, eliminating the need for reactive feedback that introduces delay. The phase rotator prepares the signal with anticipated phase corrections based on the DPLL's error measurements.
3Ease of manufacture
If low cost crystals are used with strict control, then cost is reduced, but phase noise control becomes more difficult
Solution Approach 1:
The patent implements self-service by enabling the system to automatically compensate for phase noise using the phase error metric generated by the DPLL. The phase rotator uses this metric to self-correct phase deviations, eliminating the need for expensive high-precision crystals while maintaining control precision through digital processing.
Data Source
AI summary
The present disclosure relates to methods and apparatuses for compensating carrier or clock signal phase fluctuations. An apparatus comprises a digital phase locked loop (210) comprising a phase error output (214) for a phase error (216) between a reference signal (218) and an output signal (212) generated by the digital phase locked loop, and a phase rotator (220) coupled to the phase error output (214) and configured to rotate a phase of a data signal based on the phase error (216).