Digital Pixel Sensor ADC Readout for Complete Charge Transfer
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Solution Overview
Problem
Digital Pixel Sensors (DPS) systems face challenges in achieving full charge transfer due to scaling pixel size, leading to noise, fill factor, and lag issues, and require complex readout procedures with additional wires that disturb small pixel sizes.
Innovation Solution
The implementation of an image sensor system with active pixels coupled to an analog-to-digital conversion (ADC) unit, featuring two transfer gates for two-way charge transfer, and a pixel circuit with a photodiode region and floating diffusion region for optimized charge movement, along with a method for forming semiconductor devices with specific implant layers and transfer gates for electron drift current generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is scaled down to increase resolution, then image detail and resolution are improved, but charge transfer completeness deteriorates leading to noise and lag issues
Solution Approach 1:
The pixel region is divided into multiple charge wells (first charge well, second charge well, third charge well) that can independently transfer charge to different floating diffusion regions. This segmentation allows each well to be optimally sized for complete charge transfer while maintaining high overall resolution through the combined array of segmented pixels.
2Reliability
If complex readout procedures with independent control signals are implemented to achieve full charge transfer, then charge transfer completeness is improved, but device complexity increases due to additional wires
Solution Approach 1:
Multiple charge transfer operations are merged into a single unified readout procedure. The transfer gates are controlled simultaneously by one readout control signal, combining what would otherwise require multiple independent control signals into a single coordinated operation that maintains complete charge transfer while reducing control complexity.
Solution Approach 2:
The transfer gates serve multiple functions: they enable charge transfer from different charge wells to different floating diffusion regions, support both photoelectric conversion and time-of-flight measurements, and can be controlled by a universal readout control signal that manages all transfer operations simultaneously, reducing the need for separate control circuits.
3Measurement precision
If additional wires are added for independent readout control of flag bits, then readout control precision is improved, but pixel size is reduced due to space constraints
Solution Approach 1:
The flag bit readout is merged with the ADC data bit readout into a single unified readout process. Both the flag bit and ADC data bits are read out simultaneously through the same control signal and wiring infrastructure, eliminating the need for separate control wires that would otherwise be required for independent flag bit readout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables complete charge transfer, reducing image lag and improving noise performance while simplifying readout procedures, allowing for smaller pixel sizes without disturbing the DPS system.
Implementation Method 1
configured for causing an electron drift current from a first side of the pixel region to a second side of the pixel region thereby providing the two-way charge transfer based on an operation of the first and second transfer gates
Implementation Method 2
Digital Pixel Sensors (DPS) used for image sensing applications
Data Source
AI summary
Some embodiments relate to an imaging system including an active pixel and an analog-to-digital conversion (ADC) circuit including comparator. The comparator may be operatively coupled to the active pixel and configured to receive an output of the active pixel. The back-end ADC and memory circuit may be operatively coupled to the active pixel. The back-end ADC and memory circuit may include a write control circuit, an ADC memory operatively coupled to a read/write data bus and to the write control circuit, and a state latch operatively coupled to the write control circuit.