Digital Pixel Analog Counter with Pulsed Charge Accumulation
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Solution Overview
Problem
Legacy analog imagers face challenges in maintaining high Signal-to-Noise Ratio (SNR) due to shrinking pixel sizes, which is exacerbated by the disproportionate reduction in well capacitor size, necessitating improved charge handling and integration methods.
Innovation Solution
The implementation of an analog counter circuit that utilizes time-delayed reset pulses and feedback capacitors to control charge accumulation and removal, ensuring consistent and efficient charge transfer to an accumulating capacitor, thereby enhancing SNR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to increase resolution, then imaging resolution is improved, but well capacitor size is reduced disproportionately causing degraded SNR
Solution Approach 1:
The patent divides the integration function into multiple segments: a small integration capacitor for rapid charge accumulation and a larger accumulating capacitor for final charge storage. The analog counter circuit segments the charge transfer process into discrete steps, allowing the system to maintain high SNR by accumulating charge on the larger capacitor while keeping the integration capacitor small for fast response.
Solution Approach 2:
The patent introduces an analog counter circuit as an intermediary between the integration capacitor and the accumulating capacitor. This intermediary circuit includes transfer switches and control logic that mediate the charge transfer process, ensuring complete and controlled charge transfer from the small integration capacitor to the larger accumulating capacitor, thereby maintaining SNR despite reduced pixel size.
2Speed
If integration capacitor size is reduced for faster response, then response speed is improved, but charge accumulation capacity is reduced causing degraded SNR
Solution Approach 1:
The patent segments the capacitor system into two distinct components: a small integration capacitor (115) for fast charge accumulation and a larger accumulating capacitor (308) for high-capacity storage. The analog counter circuit manages the transfer between these segments, allowing the small integration capacitor to respond quickly to incoming photocharge while the larger accumulating capacitor ensures sufficient charge accumulation capacity for high SNR.
Solution Approach 2:
The patent implements preliminary charge accumulation on the small integration capacitor during the integration period, then uses the analog counter circuit to transfer this pre-accumulated charge to the larger accumulating capacitor. This preliminary action on the small capacitor enables fast response, while the subsequent transfer to the larger capacitor ensures adequate charge capacity.
3Loss of time
If asynchronous comparator reset is used for immediate response, then response time is improved, but charge transfer precision is reduced causing increased leakage
Solution Approach 1:
The patent implements feedback control in the analog counter circuit, where the state of the accumulating capacitor and transfer switches is monitored and used to control subsequent charge transfer operations. This feedback mechanism ensures that charge is transferred only when appropriate conditions are met, preventing leakage and ensuring precise charge transfer while maintaining the benefits of asynchronous operation.
Solution Approach 2:
The patent uses periodic control signals to manage the transfer switches in the analog counter circuit. The control logic generates periodic enable signals that activate transfer switches at appropriate times, ensuring synchronized and precise charge transfer from the integration capacitor to the accumulating capacitor, thereby reducing leakage while maintaining fast response.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved SNR by ensuring consistent charge accumulation and reduced leakage, maintaining high accuracy and performance even with smaller pixel sizes.
Implementation Method 1
the feedback capacitor removes charge from a floating node
Implementation Method 2
a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP)
Implementation Method 3
a control switch connected between a source voltage and a floating node, wherein the control switch is controlled by the signal RP* on the first inverter output
Data Source
AI summary
An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor.