Digital Pixel Exposure Using Multiple Ramp Voltages
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Solution Overview
Problem
Prior digital pixel sensors using Pulse Width Modulation (PWM) face limitations in dynamic range due to inconsistent reference voltage ramp changing rates during reset and integration sampling periods, leading to incomplete elimination of reset noise and offsets, especially in natural light environments.
Innovation Solution
A digital pixel exposure method utilizing multiple ramp voltages as reference voltages, where the integration sampling period is divided into sub-periods with consistent ramp rising rates, ensuring that the reference voltage changes match the rates of the reset sampling period, thereby eliminating reset noise and offsets effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reference voltage is used during both reset and integration sampling periods, then the device complexity is reduced, but the measurement precision deteriorates due to inability to eliminate reset noise and offsets
Solution Approach 1:
The patent divides the integration sampling period into multiple sub-periods (first integration sampling sub-period, second integration sampling sub-period, etc.), each with its own reference voltage ramp signal. This segmentation allows different reference voltages to be applied at different times, enabling effective elimination of reset noise and offsets while maintaining manageable device complexity through systematic design.
2Measurement precision
If the integration sampling period is divided into multiple sub-periods with different reference voltages, then the measurement precision improves by eliminating reset noise and offsets, but the device complexity increases
Solution Approach 1:
The patent employs dynamic reference voltage ramp signals that change over time within each sub-period. The reference voltage ramps up during the rising period and holds constant during the holding period, creating a dynamic reference that adapts to different sampling requirements. This dynamic approach enables precise noise elimination without requiring completely separate reference voltage generation circuits for each sub-period.
3Device complexity
If the reference voltage ramp changing rate is inconsistent between reset and integration sampling periods, then the device complexity is reduced, but the measurement precision deteriorates due to incomplete elimination of reset noise and offsets
Solution Approach 1:
The patent carefully controls the ramp changing rates of reference voltages during different periods. By adjusting the ramp slope parameters to be consistent between the reset sampling period and integration sampling sub-periods, the system achieves complete elimination of reset noise and offsets. This parameter matching is achieved through coordinated control of the reference voltage generation circuits without requiring overly complex control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent reference voltage changing rates across both sampling periods, effectively eliminating reset noise and offsets, thereby enhancing the dynamic range and accuracy of light intensity detection in digital pixel sensors.
Implementation Method 1
the photodiode capacitor is discharged by photocurrent generated by light
Data Source
AI summary
The present invention relates to a CMOS image sensor. The present invention provides a digital pixel sensor capable of maintaining consistency between two reference voltage changing rates. To this end, the invention proposes a technical solution in which a digital pixel exposure method by using multiple ramp voltage as reference voltage is provided. Said method includes the following steps: by means of PWM pixel array, a PWM pixel is composed of a photodiode PD, a reset transistor MRST, a pixel or column level comparator, and a pixel or column or array level memory; the two input ends of the pixel level comparator are connected with PD node voltage and a predefined reference voltage Vref; after being reset, the PWM type digital pixel undergoes an exposure period; the exposure time includes a reset sampling period Trs and an integration sampling period Tis; in resetting sampling period, reference voltage Vref linearly rises from Vref_rsl to Vref_rsh; The integration sampling period is divided into several sub periods. The present invention mainly applies to design and manufacture of CMOS image sensors.