Digital Pixel Sensor Readout With Integrated Flag and ADC Data
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Solution Overview
Problem
Digital Pixel Sensors (DPS) systems face challenges in achieving full charge transfer due to scaling pixel size, leading to noise, fill factor, and lag issues, and require complex readout procedures with additional wires that disturb small pixel sizes, especially due to the separation of flag bits from analog-to-digital conversion data bits.
Innovation Solution
The implementation of an image sensor system with active pixels coupled to an analog-to-digital converter (ADC) that includes a comparator, memory, and a write control circuit, featuring two transfer gates for two-way charge transfer, optimizing charge movement from the photodiode to the floating diffusion region, and a method for determining physical distances using indirect time-of-flight measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is scaled down to increase resolution, then image quality and resolution are improved, but charge transfer completeness deteriorates leading to noise and lag issues
Solution Approach 1:
The photodiode region is divided into multiple segments (first photodiode region and second photodiode region) with corresponding transfer gates. This segmentation allows independent charge transfer control from different regions, ensuring complete charge transfer even in scaled-down pixels by preventing charge loss in any single region.
Solution Approach 2:
Instead of using a single transfer gate that transfers charge in one direction, the patent implements bidirectional charge transfer capability by configuring transfer gates that can transfer charges from both the first and second photodiode regions to the floating diffusion region. This inversion of the traditional unidirectional approach ensures no charge is left behind in either region.
2Measurement precision
If complex readout procedure with separate flag bit is implemented, then data accuracy is improved, but device complexity increases requiring additional wires
Solution Approach 1:
The patent combines the flag bit and ADC data bit into a unified readout structure where the same transfer gate control signals serve both the charge transfer function and the data readout function. This merging eliminates the need for separate independent readout control signals for the flag bit, reducing wire requirements while maintaining data accuracy.
Solution Approach 2:
The transfer gates are designed to perform multiple functions: they control charge transfer from photodiode regions to the floating diffusion region, and simultaneously control the readout of both flag bit and ADC data bits. This multi-functionality reduces the overall number of control wires needed while preserving data accuracy through proper timing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables complete charge transfer, reducing image lag and noise, and simplifies the readout process by integrating the flag bit with ADC data, reducing the number of wires needed and improving the performance of DPS systems, especially in small pixel sizes.
Implementation Method 1
a first transfer gate and a second transfer gate having first poly layer and a first charge well layer and are configured for causing an electron drift current from a first side of the pixel region to a second side of the pixel region
Data Source
AI summary
Some embodiments relate to an imaging system including an active pixel a comparator, a write control circuit, and an analog-to-digital conversion (ADC) memory. The active pixel may include a photodiode and a plurality of transistors. The comparator may be operative coupled to the active pixel and configured to receive an output of the active pixel. The write control circuit may be operative coupled to the comparator and configured to receive an output from the comparator. The ADC memory may be operatively coupled to the write control circuit. A data structure may be stored in the ADC memory, and may be configured to store at least a first data string, which may include a set of flag bits for identifying each ADC operation performed and a set of ADC data bits.