Digital Pixel Architecture for Parallel Residue ADC Conversion

The pixel array is divided into multiple rows, each with its own integration capacitor and digitization components. This segmentation allows each row to independently perform analog-to-digital conversion of its residue signal, enabling parallel processing across multiple rows simultaneously, thereby increasing frame rate and reducing the time loss associated with sequential digitization.

The patent combines multiple functions within each pixel circuit: the integration capacitor serves both for signal integration during the exposure period and for residue storage during digitization. The comparator and counter components are reused for both primary signal digitization and residue digitization. This merging of functions eliminates the need for separate column-parallel analog-to-digital converters, enabling faster parallel processing and improving frame rate.

Each pixel circuit is designed as a universal unit that can perform multiple operations: integrating the optical signal, comparing the integrated voltage against a reference, counting the comparison cycles, and then reusing the same components to digitize the residue signal. This multi-functionality allows parallel processing across pixels without requiring separate dedicated hardware for each digitization task, thus increasing processing speed while controlling hardware complexity.

The pixel circuit dynamically reconfigures its operation modes: during the exposure period, it integrates signals; during the first digitization phase, it performs comparator-based counting; and during the residue digitization phase, it applies ramp voltage and performs second counting. This dynamic reconfiguration allows the same hardware to adapt to different processing stages, enabling faster overall processing without permanently increasing hardware complexity.