Digital PLL Bandwidth Switching for Fast Lock and Low Jitter
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Solution Overview
Problem
Existing phase locked loop (PLL) circuits face challenges in achieving fast settling times over a wide frequency range while maintaining stability and reducing jitter, often requiring impractically high bandwidth.
Innovation Solution
A digital PLL system that includes a phase locked loop circuit coupled with a digital control unit, utilizing a time-to-digital converter, digital loop filter, digitally controlled oscillator, and divider circuit, which dynamically adjusts gain coefficients and N/R values to achieve fast settling times by initially increasing bandwidth for rapid phase acquisition and then scaling it back for reduced noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If PLL bandwidth is increased to achieve fast settling time, then settling time is reduced, but implementation difficulty increases and performance deteriorates
Solution Approach 1:
The patent implements dynamic bandwidth adjustment by switching between a first bandwidth (higher) during frequency transitions and a second bandwidth (lower) during steady-state operation. This is achieved through a control mechanism that monitors PLL lock status and automatically adjusts the loop filter coefficients, allowing the system to optimize settling performance without requiring permanently high bandwidth that would increase implementation complexity and degrade overall performance.
Solution Approach 2:
The patent changes the bandwidth parameter dynamically based on operational conditions. By adjusting loop filter coefficients (Kp and Ki) according to lock status, the system transitions between different bandwidth states. This parameter change approach enables fast settling during frequency changes while maintaining stable, low-noise operation during steady state, resolving the contradiction between fast settling and implementation complexity.
2Speed
If PLL bandwidth is increased to achieve fast settling time, then phase acquisition speed is improved, but jitter performance deteriorates
Solution Approach 1:
The patent employs dynamic bandwidth adjustment where a higher first bandwidth is used during frequency transitions to accelerate phase acquisition, and a lower second bandwidth is used during steady-state operation to minimize jitter. The control mechanism switches between these bandwidth states based on lock detection, thereby achieving both fast phase acquisition and low jitter performance without the trade-offs of a fixed high-bandwidth design.
Solution Approach 2:
The patent implements periodic switching between different bandwidth configurations based on the PLL lock status. During frequency transitions, the system operates with higher bandwidth for rapid acquisition; once locked, it switches to lower bandwidth for reduced jitter. This periodic action between different operational modes enables the system to achieve both fast phase acquisition and low jitter, resolving the contradiction between speed and reliability.
3Productivity
If PLL bandwidth is increased to achieve fast settling time, then frequency response is improved, but stability margin is reduced
Solution Approach 1:
The patent implements dynamic bandwidth adjustment that uses a higher first bandwidth during frequency transitions to improve frequency response and settling speed, then switches to a lower second bandwidth during steady-state operation to maintain adequate stability margins. This dynamic approach allows the system to achieve fast frequency response when needed without permanently compromising stability, resolving the contradiction between productivity and stability.
Solution Approach 2:
The patent changes the bandwidth parameter dynamically by adjusting loop filter coefficients based on operational phase. During frequency transitions, higher bandwidth parameters are applied for improved frequency response; during steady state, lower bandwidth parameters are applied to maintain stability margins. This parameter change strategy enables the system to achieve both fast frequency response and adequate stability, resolving the technical contradiction.
Data Source
AI summary
A method includes receiving data for a desired output frequency of an output clock of a phase locked loop (PLL) circuit. The method includes determining a preset value for a digitally controlled oscillator (DCO) of the PLL circuit, determining first gain coefficients and second gain coefficients for a filter of the PLL circuit, and determining ratio values for a divider circuit of the PLL circuit based on the data. The method includes providing the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration. The method includes subsequently operating the PLL circuit in a closed-loop configuration by connecting the filter to the DCO, and providing the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.