Digital PLL Frequency Synthesizer for Nanosecond Channel Hopping
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) are unsuitable for frequency-hopping systems in mobile communication, particularly in ultra-wide band (UWB) applications, as they require several microseconds to settle on a new channel, which is too slow for nanosecond frequency changes, and generating additional low-frequency signals consumes more power and chip area.
Innovation Solution
A frequency-hopping synthesizer with a digital phase-locked loop that pre-programmes and stores internal states for each desired frequency, allowing the circuit to resume operation from a settled state, reducing the need for re-locking and minimizing power consumption by eliminating the need for a periodically addressed read-only memory with a digital-to-analog converter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional phase-locked loop is used for frequency synthesis, then the circuit structure is simple, but the settling time is too long (several microseconds) to meet nanosecond frequency switching requirements
Solution Approach 1:
The patent pre-calculates and stores the internal states of the loop filter for each desired frequency channel in a memory device. When frequency hopping is required, the corresponding pre-stored internal state is immediately loaded into the loop filter, allowing the PLL to resume from a settled state rather than undergoing a complete settling process. This preliminary preparation of states eliminates the microsecond settling delay and enables nanosecond-scale frequency switching.
2Adaptability or versatility
If additional low-frequency signals are generated using a periodically addressed ROM and digital-to-analog converter, then frequency hopping capability is achieved, but power consumption and chip area increase
Solution Approach 1:
The patent extracts and eliminates the digital-to-analog converter and periodically addressed ROM from the system by implementing a fully digital loop filter. The internal states are stored and manipulated in digital form within the loop filter and memory, removing the need for additional low-frequency signal generation hardware. This extraction reduces both power consumption and chip area while maintaining frequency hopping capability through digital state manipulation.
3Adaptability or versatility
If additional low-frequency signals are generated using a periodically addressed ROM and digital-to-analog converter, then frequency hopping capability is achieved, but chip area is occupied
Solution Approach 1:
The patent merges the frequency hopping functionality into the existing phase-locked loop structure by implementing a digital loop filter that can load different internal states from memory. Instead of adding separate signal generation paths with ROM and DAC, the frequency hopping capability is integrated directly into the PLL's control mechanism through digital state manipulation. This merging approach achieves frequency hopping without occupying additional chip area for separate components.
Data Source
AI summary
A synthesizer arrangement includes an oscillator, a phase detector, and a loop filter that form a phase-locked loop. The loop filter is coupled to a control unit to activate a respective set of internal states out of a plurality of sets of internal states.