Digital PLL Clock Transfer for Jitter and Phase-Noise Filtering
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Solution Overview
Problem
Conventional methods for transferring high-speed clocks across digital communication devices face challenges such as high power consumption, large area requirements, and increased phase noise, which complicates meeting transmitter jitter specifications due to high jitter at the input of clock and data recovery (CDR) units.
Innovation Solution
A digital phase-locked loop (PLL) system is employed to filter and transfer phase information, using a digital PLL component that receives input phase data from a CDR unit, applies a filter to generate output phase data, and transmits it to another phase interpolator, controlling the filter based on parameters to define its function and reduce jitter and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to transfer high-speed clocks across digital communication devices, then clock transfer is achieved, but power consumption increases and area requirements expand
Solution Approach 1:
The patent replaces the conventional analog/physical clock transfer mechanism with a digital phase information transfer system. Instead of directly transferring high-speed clock signals through physical pathways, the system extracts phase information from the received signal, processes it digitally through a phase-locked loop, and reconstructs the clock at the transmitter. This substitution of mechanical/physical clock signal transfer with digital phase information processing reduces power consumption and area requirements while maintaining clock transfer reliability.
2Reliability
If conventional methods are used to transfer high-speed clocks across digital communication devices, then clock transfer is achieved, but device area increases
Solution Approach 1:
The patent replaces the conventional analog/physical clock transfer mechanism with a digital phase information transfer system. Instead of directly transferring high-speed clock signals through physical pathways, the system extracts phase information from the received signal, processes it digitally through a phase-locked loop, and reconstructs the clock at the transmitter. This substitution of mechanical/physical clock signal transfer with digital phase information processing reduces power consumption and area requirements while maintaining clock transfer reliability.
3Speed
If high-speed clocks are transferred across digital communication devices, then clock transfer is achieved, but phase noise increases and jitter specifications cannot be met
Solution Approach 1:
The patent introduces a digital phase-locked loop system as an intermediary between the received signal and the transmitter clock. This intermediary extracts phase information from the received signal, processes it through filtering and accumulation stages, and generates a clean clock signal for the transmitter. The intermediary system effectively separates the high-speed clock transfer function from the phase noise propagation, allowing speed maintenance while eliminating phase noise and jitter issues.
Solution Approach 2:
The patent implements a feedback mechanism within the digital phase-locked loop where the generated clock signal is compared with the original received signal phase information. The phase detector continuously monitors phase differences and adjusts the clock generation accordingly. This feedback loop ensures that the transmitted clock remains synchronized with the received signal while filtering out phase noise and jitter, maintaining both speed and signal quality.
Data Source
AI summary
A digital PLL, which can be a virtual PLL, can condition digital phase information, comprising phase modification requests, for transfer, jitter, and phase-noise filtering of clock information between a clock recovery unit and a clock generation unit associated with phase interpolators. The digital PLL can employ a set of accumulators, proportional and integral filter component, generator component, feedback path between the output and input of the digital PLL, and other digital signal processing components. The proportional and integral filter component can be configurable to set a loop damping factor and a loop bandwidth of the filter, based on respective parameters. Based on the filter output, the generator component can generate output phase information, comprising phase modification requests, that can be transmitted to another phase interpolator(s) associated with a transmitter or other component(s) of the device to facilitate generating a clock for the transmitter or other component(s).