Digital PLL Clock Synchronization for Packet Delay Variation
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Solution Overview
Problem
Current methods for time and frequency synchronization over packet networks, such as those using IEEE 1588 Precision Time Protocol (PTP), face challenges in achieving sub-microsecond accuracy due to packet delay variation and packet losses, which introduce clock noise and affect the precision of clock recovery mechanisms.
Innovation Solution
A digital phase locked loop (DPLL) is employed in a slave device to exchange timing messages with a master device, recording timestamps to estimate skew and offset, and synchronize the slave clock using a phase detector, loop filter, phase accumulator, and counter, thereby attenuating clock noise and providing synchronized time and frequency signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packet-based clock recovery mechanism is used to synchronize slave clock to master clock, then time synchronization can be achieved over packet networks, but packet delay variation and packet losses introduce clock noise that degrades synchronization precision
Solution Approach 1:
A phase-locked loop (PLL) is introduced as an intermediary component between the packet-based time synchronization system and the slave clock. The PLL processes the time difference measurements and generates a cleaned frequency control signal that drives the slave clock, effectively filtering out clock noise introduced by packet delay variation and losses while maintaining synchronization precision.
Solution Approach 2:
The patent replaces traditional mechanical or direct electronic clock synchronization methods with a digital signal processing approach using a phase-locked loop. The PLL converts discrete time difference measurements into a continuous frequency control signal, substituting direct clock adjustment with a feedback-controlled oscillation system that inherently filters noise.
2Measurement precision
If traditional clock synchronization methods are used, then sub-microsecond accuracy can be achieved with GPS and atomic clocks, but these methods require specialized infrastructure and do not work well over packet networks
Solution Approach 1:
The slave device performs self-synchronization by measuring time differences between received synchronization messages and its local clock, then using a phase-locked loop to automatically adjust its clock frequency. This eliminates the need for specialized GPS receivers or atomic clock infrastructure at each node, allowing standard packet network devices to achieve sub-microsecond synchronization accuracy independently.
Solution Approach 2:
The patent changes the operational parameters of clock synchronization from requiring specialized hardware (GPS receivers, atomic clocks) to using standard packet network interfaces with software-based time measurement and phase-locked loop control. This parameter change enables packet network compatibility while maintaining high precision through digital signal processing techniques.
3Adaptability or versatility
If hop-by-hop Boundary Clocks or Transparent Clocks are used for end-to-end time transfer, then clock synchronization can be achieved without network assistance, but wander propagates up to the receiver clock signal due to packet delay variation
Solution Approach 1:
The phase-locked loop implements a feedback control mechanism where the slave clock continuously measures time differences from synchronization messages, compares them against its local clock, and adjusts its frequency based on the measured error. This closed-loop feedback system prevents wander propagation by continuously correcting frequency deviations, maintaining clock signal stability while enabling independent clock recovery without network assistance.
Data Source
AI summary
This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.