All-Digital PLL Phase Control for Coherent Multi-Channel Ranging

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Solution Overview

Problem

Narrow-band radios face ambiguity in virtual-wideband channel phase state information due to multipath in non-line of sight channels, making it challenging to maintain phase coherence during ranging procedures.

Innovation Solution

An all-digital phase locked loop (ADPLL) with a pattern generator, phase accumulator, phase comparator, and controller, along with a loop filter and digitally controlled oscillator (DCO), is used to generate a predictable phase trajectory, enabling phase-coherent ranging by exchanging capacitance between capacitor banks and utilizing a two-point modulation scheme.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If narrow-band radios concatenate channels to build virtual-wideband ranging system, then ranging accuracy is improved, but phase ambiguity occurs due to multipath in non-line of sight channels

Engineering Contradiction:
Improveranging accuracyVSAvoidphase coherence
Core Design Contradiction:
Measurement precisionVSLoss of information

Solution Approach 1:

The patent implements a feedback mechanism where the ADPLL continuously monitors the phase difference between the VCO output and the reference signal, and adjusts the VCO frequency accordingly. The phase detector generates an error signal that feeds back to the loop filter, which then adjusts the VCO control voltage to maintain phase coherence across concatenated channels, resolving the phase ambiguity problem while preserving ranging accuracy.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the operating parameters of the radio system by implementing an all-digital PLL that dynamically adjusts the VCO frequency and phase across multiple narrow-band channels. By controlling the phase and frequency parameters of the ADPLL throughout the channel switching process, the system maintains predictable phase relationships and eliminates phase ambiguity in virtual-wideband ranging.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If phase coherent measurements are maintained over multiple channels, then the number of unknown parameters is reduced, but the complexity of maintaining phase coherence throughout channel switching increases

Engineering Contradiction:
Improvephase measurement accuracyVSAvoidphase coherence maintenance
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces traditional analog PLL components with an all-digital implementation. The ADPLL uses digital signal processing in the phase detector and loop filter, and digitally controls the VCO, eliminating the need for complex analog phase coherence maintenance circuits. This digital substitution simplifies the overall system while maintaining phase coherence across multiple channels.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If an all-digital phase locked loop is implemented to achieve predictable phase trajectory, then phase-based ranging coherence is improved, but the device complexity increases

Engineering Contradiction:
Improvephase coherenceVSAvoidADPLL structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the ADPLL into distinct functional blocks: a phase detector that compares the VCO output with the reference signal, a loop filter that processes the phase error, and a digital VCO that generates the output frequency. This segmentation allows each component to be optimized independently and simplifies the overall design and implementation of the phase-coherent ranging system.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11424747B2Systems and methods for all-digital phase locked loop
Publication Date: 2022.08.23 STICHTING IMEC NEDERLAND
  • US11424747B2 patent drawing
  • US11424747B2 patent drawing
  • US11424747B2 patent drawing

AI summary

An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.