Digital PLL Trigger Control for Low-Jitter CT Imaging

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Solution Overview

Problem

Conventional CT imaging systems face limitations due to slow response times of analog phase locked loops (PLLs) to input frequency variations, leading to output signal jitter and restricted rotational speed changes, which can cause scan aborts and limit diagnostic image reconstruction capabilities.

Innovation Solution

A digital phase locked loop (DPLL) system that pre-sets and locks to a desired frequency, filters output signals to minimize jitter, and interpolates triggers in real-time to maintain stability during errors, allowing for arbitrary trigger specification per gantry rotation and continuous scanning.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an analog phase locked loop is used to filter output signals, then output signal jitter is reduced, but the response time to input frequency variations becomes slow

Engineering Contradiction:
Improveoutput signal stabilityVSAvoidresponse time to frequency changes
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent replaces the analog phase locked loop with a digital phase locked loop implementation. The digital PLL uses digital filtering and processing instead of analog circuitry, enabling faster response to encoder frequency variations while maintaining output signal stability. The digital architecture allows for programmable filter characteristics and rapid adaptation to changing input conditions.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements dynamic triggering where the number of triggers per gantry rotation can be arbitrarily specified and changed during operation. The digital PLL dynamically adjusts its operation based on real-time encoder feedback, allowing the system to adapt to varying rotational speeds and trigger requirements without the limitations of fixed analog circuitry.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If the number of output pulses per gantry rotation is limited to predefined values, then system complexity is reduced, but adaptability to different imaging requirements is limited

Engineering Contradiction:
Improvetrigger configuration simplicityVSAvoidtrigger specification flexibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent enables arbitrary specification of the number of triggers per gantry rotation by changing the digital parameters in the PLL. Instead of being constrained to fixed values determined by hardware dividers, the system allows any integer value to be programmed, providing flexibility for different imaging protocols while maintaining simple operation through software configuration.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If communication errors occur between the encoder and PLL, then scan stability is compromised, but error detection capability is improved

Engineering Contradiction:
Improveerror detection accuracyVSAvoidscan continuity
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent implements a feedback mechanism where the digital PLL continuously monitors encoder pulses and detects communication errors. When errors are detected, the system can interpolate missing trigger signals based on the expected timing pattern, allowing the scan to continue without interruption while maintaining accurate synchronization.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system prepares for potential communication errors by having the digital PLL ready to interpolate missing trigger signals. This preemptive approach ensures that if encoder pulses are lost or corrupted, the system can recover and maintain scan continuity without requiring manual intervention or scan abort.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS8085075B2Method and system for diagnostic imaging using a digital phase locked loop
Publication Date: 2011.12.27 GENERAL ELECTRIC CO
  • US8085075B2 patent drawing
  • US8085075B2 patent drawing
  • US8085075B2 patent drawing

AI summary

A method and apparatus are provided for minimizing output pulse jitters in a phase locked loop. The method includes pre-setting the digital phase locked loop to a desired frequency, locking the digital phase locked loop to the desired frequency to generate an output signal, and filtering the output signal of the digital phase locked loop to maintain undesirable jitter to an acceptable range. In one embodiment, the apparatus is a medical imaging device. In another embodiment, the apparatus is a baggage imaging device.